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CoPA: Cold page awakening to overcome retention failures in STT-MRAM Based I/O Buffers
, Article IEEE Transactions on Parallel and Distributed Systems ; Volume 33, Issue 10 , 2022 , Pages 2304-2317 ; 10459219 (ISSN) ; Cheshmikhani, E ; Rahmanpour, M ; Mutlu, O ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2022
Abstract
Performance and reliability are two prominent factors in the design of data storage systems. To achieve higher performance, recently storage system designers use DynamicDynamic RAMRAM (DRAM)-based buffers. The volatility of DRAM brings up the possibility of data loss and data inconsistency. Thus, a part of the main storage is conventionally used as the journal area to be able of recovering unflushed data pages in the case of power failure. Moreover, periodically flushing buffered data pages to the main storage is a common mechanism to preserve a high level of reliability. This scheme, however, leads to a considerable increase in storage write traffic, which adversely affects the performance....
PIPF-DRAM: Processing in precharge-free DRAM
, Article 59th ACM/IEEE Design Automation Conference, DAC 2022, 10 July 2022 through 14 July 2022 ; 2022 , Pages 1075-1080 ; 0738100X (ISSN); 9781450391429 (ISBN) ; Soleimani, M. A ; Sarbazi Azad, H ; ACM Special Interest Group on Design Automation (SIGDA); IEEE CEDA ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2022
Abstract
To alleviate costly data communication among processing cores and memory modules, parallel processing-in-memory (PIM) is a promising approach which exploits the huge available internal memory bandwidth. High capacity, wide row size, and maturity of DRAM technology, make DRAM an alluring structure for PIM. However, dense layout, high process variation, and noise vulnerability of DRAMs make it very challenging to apply PIM for DRAMs in practice. This work proposes a PIM structure which eliminates these DRAM limitations, exploiting a precharge-free DRAM (PF-DRAM) structure. The proposed PIM structure, called PIPF-DRAM, performs parallel bitwise operations only by modifying control signal...
PF-DRAM: A precharge-free DRAM structure
, Article 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, 14 June 2021 through 19 June 2021 ; Volume 2021-June , 2021 , Pages 126-138 ; 10636897 (ISSN); 9781665433334 (ISBN) ; Darabi, S ; Sarbazi Azad, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2021
Abstract
Although DRAM capacity and bandwidth have increased sharply by the advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. The main portion of DRAM power/energy is dissipated by Read, Write, and Refresh operations, all initiated by a Precharge phase. Precharge phase not only imposes a large amount of energy consumption, but also increases the delay of closing a row in a memory block to open another one. By reduction of row-hit rate in recent workloads, especially in multi-core systems, precharge rate increases which exacerbates DRAM power dissipation and access latency. This work proposes a novel DRAM structure, called...
ETICA: Efficient two-level I/O caching architecture for virtualized platforms
, Article IEEE Transactions on Parallel and Distributed Systems ; Volume 32, Issue 10 , 2021 , Pages 2415-2433 ; 10459219 (ISSN) ; Salkhordeh, R ; Mutlu, O ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2021
Abstract
In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: They support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of...
Evaluating reliability of SSD-Based I/O caches in enterprise storage systems
, Article IEEE Transactions on Emerging Topics in Computing ; Volume 9, Issue 4 , 2021 , Pages 1914-1929 ; 21686750 (ISSN) ; Taheri, F ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2021
Abstract
I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and non-volatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss...
Etica: Efficient Two-Level I/O caching architecture for virtualized platforms
, Article IEEE Transactions on Parallel and Distributed Systems ; Volume 32, Issue 10 , 2021 , Pages 2415-2433 ; 10459219 (ISSN) ; Salkhordeh, R ; Mutlu, O ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2021
Abstract
In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: They support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of...
Evaluating reliability of SSD-Based I/O caches in enterprise storage systems
, Article IEEE Transactions on Emerging Topics in Computing ; Volume 9, Issue 4 , 2021 , Pages 1914-1929 ; 21686750 (ISSN) ; Taheri, F ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2021
Abstract
I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and non-volatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss...
CoPA: Cold page awakening to overcome retention failures in Stt-Mram based I/O buffers
, Article IEEE Transactions on Parallel and Distributed Systems ; 2021 ; 10459219 (ISSN) ; Cheshmikhani, E ; Rahmanpour, M ; Mutlu, O ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2021
Abstract
Employing a small Non-Volatile Memory (NVM) as the Persistent Journal Area (PJA) along with a DRAM-based buffer is an efficient approach to overcome DRAM vulnerability, named NVB-Buffer. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising PJA candidates thanks to providing high endurance, non-volatility, and DRAM-like latency. Despite these advantages, STT-MRAM faces major reliability challenges, i.e. Retention Failure, Read Disturbance, and Write Failure, which have not been addressed in previously suggested NVB-Buffers. In this paper, we first demonstrate that the retention failure is the dominant source of errors in NVB-Buffers as it suffers from...
STAIR: high reliable STT-MRAM aware multi-level I/O cache architecture by adaptive ECC allocation
, Article 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, 9 March 2020 through 13 March 2020 ; 2020 , Pages 1484-1489 ; Cheshmikhani, E ; Asadi, H ; ACM Special Interest Group on Design Automation (SIGDA); et al.; European Design and Automation Association (EDAA); European Electronic Chips and Systems Design Initiative (ECSI); IEEE Council on Electronic Design Automation (CEDA); SEMI Strategic Technology Community and Electronic System Design Alliance (ESD Alliance) ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2020
Abstract
Hybrid Multi-Level Cache Architectures (HCAs) are promising solutions for the growing need of high-performance and cost-efficient data storage systems. HCAs employ a high endurable memory as the first-level cache and a Solid-State Drive (SSD) as the second-level cache. Spin-Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising candidates for the first-level cache of HCAs because of its high endurance and DRAM-comparable performance along with non-volatility. However, STT-MRAM faces with three major reliability challenges named Read Disturbance, Write Failure, and Retention Failure. To provide a reliable HCA, the reliability challenges of STT-MRAM should be carefully addressed....
An analytical model for performance and lifetime estimation of hybrid DRAM-NVM main memories
, Article IEEE Transactions on Computers ; Volume 68, Issue 8 , 2019 , Pages 1114-1130 ; 00189340 (ISSN) ; Mutlu, O ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2019
Abstract
Emerging Non-Volatile Memories (NVMs) have promising advantages (e.g., lower idle power, higher density, and non-volatility) over the existing predominant main memory technology, DRAM. Yet, NVMs also have disadvantages (e.g., longer latencies, higher active power, and limited endurance). System architects are therefore examining hybrid DRAM-NVM main memories to enable the advantages of NVMs while avoiding the disadvantages as much as possible. Unfortunately, the hybrid memory design space is very large and complex due to the existence of very different types of NVMs and their rapidly-changing characteristics. Therefore, optimization of performance and lifetime of hybrid memory based...
An efficient hybrid I/O caching architecture using heterogeneous SSDs
, Article IEEE Transactions on Parallel and Distributed Systems ; Volume 30, Issue 6 , 2019 , Pages 1238-1250 ; 10459219 (ISSN) ; Hadizadeh, M ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2019
Abstract
Storage subsystem is considered as the performance bottleneck of computer systems in data-intensive applications. Solid-State Drives (SSDs) are emerging storage devices which unlike Hard Disk Drives (HDDs), do not have mechanical parts and therefore, have superior performance compared to HDDs. Due to the high cost of SSDs, entirely replacing HDDs with SSDs is not economically justified. Additionally, SSDs can endure a limited number of writes before failing. To mitigate the shortcomings of SSDs while taking advantage of their high performance, SSD caching is practiced in both academia and industry. Previously proposed caching architectures have only focused on either performance or endurance...
Bingo spatial data prefetcher
, Article 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, 16 February 2019 through 20 February 2019 ; 2019 , Pages 399-411 ; 9781728114446 (ISBN) ; Shakerinava, M ; Lotfi Kamran, P ; Sarbazi Azad, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
Applications extensively use data objects with a regular and fixed layout, which leads to the recurrence of access patterns over memory regions. Spatial data prefetching techniques exploit this phenomenon to prefetch future memory references and hide the long latency of DRAM accesses. While state-of-the-art spatial data prefetchers are effective at reducing the number of data misses, we observe that there is still significant room for improvement. To select an access pattern for prefetching, existing spatial prefetchers associate observed access patterns to either a short event with a high probability of recurrence or a long event with a low probability of recurrence. Consequently, the...
Evaluating reliability of SSD-Based I/O caches in enterprise storage systems
, Article IEEE Transactions on Emerging Topics in Computing ; 2019 ; 21686750 (ISSN) ; Taheri, F ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2019
Abstract
I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss...
Reducing writebacks through in-cache displacement
, Article ACM Transactions on Design Automation of Electronic Systems ; Volume 24, Issue 2 , 2019 ; 10844309 (ISSN) ; Faraji, A ; Vakil Ghahani, S. A ; Samandi, F ; Lotfi Kamran, P ; Sarbazi Azad, H ; Sharif University of Technology
Association for Computing Machinery
2019
Abstract
Non-Volatile Memory (NVM) technology is a promising solution to fulfill the ever-growing need for higher capacity in the main memory of modern systems. Despite having many great features, however, NVM's poor write performance remains a severe obstacle, preventing it from being used as a DRAM alternative in the main memory. Most of the prior work targeted optimizing writes at the main memory side and neglected the decisive role of upper-level cache management policies on reducing the number of writes. In this article, we propose a novel cache management policy that attempts to maximize write-coalescing in the on-chip SRAM last-level cache (LLC) for the sake of reducing the number of costly...
Evaluating reliability of SSD-Based I/O caches in enterprise storage systems
, Article IEEE Transactions on Emerging Topics in Computing ; 2019 ; 21686750 (ISSN) ; Taheri, F ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2019
Abstract
I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss...
ECI-cache: a high-endurance and cost-efficient I/O caching scheme for virtualized platforms
, Article SIGMETRICS 2018 - Abstracts of the 2018 ACM International Conference on Measurement and Modeling of Computer Systems ; 12 June , 2018 , Pages 73- ; 9781450358460 (ISBN) ; Mutlu, O ; Asadi, H ; Sharif University of Technology
Association for Computing Machinery, Inc
2018
Abstract
In recent years, high interest in using Virtual Machines (VMs) in data centers and cloud computing has significantly increased the demand for high-performance data storage systems. A straightforward approach to providing a high-performance storage system is using Solid-State Drives (SSDs). Inclusion of SSDs in storage systems, however, imposes significantly higher cost compared to Hard Disk Drives (HDDs). Recent studies suggest using SSDs as a caching layer for HDD-based storage subsystems in virtualized platforms. Such studies neglect to address the endurance and cost of SSDs, which can significantly affect the efficiency of I/O caching. Moreover, previous studies only configure the cache...
Improving MLC PCM performance through relaxed write and read for intermediate resistance levels
, Article ACM Transactions on Architecture and Code Optimization ; Volume 15, Issue 1 , 2018 ; 15443566 (ISSN) ; Jalili, M ; Sarbazi Azad, H ; Sharif University of Technology
Association for Computing Machinery
2018
Abstract
Phase Change Memory (PCM) is one of the most promising candidates to be used at the main memory level of the memory hierarchy due to poor scalability, considerable leakage power, and high cost/bit of DRAM. PCM is a new resistive memory that is capable of storing data based on resistance values. The wide resistance range of PCM allows for storing multiple bits per cell (MLC) rather than a single bit per cell (SLC). Unfortunately, higher density of MLC PCM comes at the expense of longer read/write latency, higher soft error rate, higher energy consumption, and earlier wearout compared to the SLC PCM. Some studies suggest removing the most error-prone level to mitigate soft error and write...
Express read in MLC phase change memories
, Article ACM Transactions on Design Automation of Electronic Systems ; Volume 23, Issue 3 , February , 2018 ; 10844309 (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
Association for Computing Machinery
2018
Abstract
In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and...
Tolerating more hard errors in MLC PCMs using compression
, Article Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016, 2 October 2016 through 5 October 2016 ; 2016 , Pages 304-311 ; 9781509051427 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Modern computer systems require fast, large and reliable memories to handle information explosion. With this goal in mind, not only deployment of main memories with new technologies are necessary, but also adopting innovative solutions for addressing newfound challenges must be considered as a priority. Recently, phase change memory (PCM) appeared as a preferred candidate for substituting DRAM. PCM with non-volatility, low static power consumption and storing multiple level cells (MLC) capability has opened a new way to the future of memories. Although PCM presents considerable potentials, its short lifetime is a critical concern. Worse still, adopting multiple bits per cell capability...
BLESS: A simple and efficient scheme for prolonging PCM lifetime
, Article 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, 5 June 2016 through 9 June 2016 ; Volume 05-09 , June-2016 , 2016 ; 0738100X (ISSN); 9781450342360 (ISBN) ; Jalili, M ; Sarbazi Azad, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Limited endurance problem and low cell reliability are main challenges of phase change memory (PCM) as an alternative to DRAM. To further prolong the lifetime of a PCM device, there exist a number of techniques that can be grouped in two categories: 1) reducing the write rate to PCM cells, and 2) handling cell failures when faults occur. Our experiments confirm that during write operations, an extensive non-uniformity in bit ips is exhibited. To reduce this non-uniformity, we present byte-level shifting scheme (BLESS) which reduces write pressure over hot cells of blocks. Additionally, this shifting mechanism can be used for error recovery purpose by using the MLC capability of PCM and...