Sharif Digital Repository

By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities... 

Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require working with decimal numbers while it has been shown that if we convert decimal number to binary ones, this will negatively influence the preciseness required for these applications. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today's digital systems. While the energy consumption of parallel decimal multipliers has not been addressed in previous works, in this paper we present a comparative study of... 

Decimal arithmetic has gained intensive attention in the last decade. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system loses preciseness in some cases. The latency and area are two major factors in existing research works on decimal multiplication. However, energy/power consumption is another important factor in today's digital systems. Hence, in this paper we proposed a new low power decimal adder based on prediction technique for decreasing the energy/power consumption of parallel decimal multiplication and show its impacts on one of the well-known parallel decimal multipliers architecture. Our observations... 

Recently, the tradeoff between low energy consumption and high fault-tolerance has attracted a lot of attention as a key issue in the design of real-time systems. Dynamic Voltage Scaling (DVS) is commonly employed as one of the most effective low energy techniques for real-time systems. It has been observed that the use of feedback-based methods can improve the effectiveness of DVS-enabled systems. In this paper, we have investigated reducing the energy consumption of fault-tolerant hard real-time systems using the feedback control theory. Our proposed method makes the system capable of selecting the proper frequency and voltage settings in order to reduce the energy consumption, while... 

Estimating the energy consumption of applications is a key aspect in optimizing embedded systems energy consumption. This paper proposes a simple yet accurate instruction-level energy estimation model for embedded systems. As a case study, the model parameters were determined for a commonly used ARM7TDMI-based microcontroller. The total energy includes the energy consumption of the processor core, Flash memory, memory controller, and SRAM. The model parameters are instructions opcode, number of shift operations, register bank bit flips, instructions weight and their Hamming distance, and different types of memory accesses. Also, the effect of pipeline stalls have been considered. In order to... 

To scavenge the energy from the environment and extend the network lifetime, some wireless sensor networks (WSNs) have been equipped with energy harvesters recently. However, the variable amount of environmental energy can affect the reliability of energy harvesting wireless sensor networks (EH-WSNs). In addition, data transmission over a wireless media is vulnerable. Hence, utilizing suitable error control schemes are necessary to improve the reliability. Regarding this point, Automatic Repeat Request (ARQ) and Cooperative ARQ (C-ARQ) schemes are applied in this generation of WSNs. Conventional ARQ as well as C-ARQ scheme are considered and examined through simulation. A comparative... 

Energy harvesters are used in today's Wireless Sensor Networks (WSNs) to harvest energy from the environment. Although an energy harvester can provide a supply source with a much greater lifetime than a battery, the amount of available energy for an energy harvesting system is a random variable. Furthermore, the proper management of energy harvesters has a considerable impact on reliability. It has been observed that cooperative error control mechanisms like Cooperative Automatic Repeat Request (C-ARQ) and Cooperative Hybrid ARQ (C-HARQ) can be used for improving the energy management and reliability in Energy Harvesting WSNs (EH-WSNs). Recently, the impact of C-ARC mechanism has been... 

In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

The interaction between fault tolerance and energy consumption is an interesting avenue in the realm of designing embedded systems. In this paper, a scheme for reducing energy consumption in conventional standby-sparing systems is introduced. In the proposed method, the primary unit exploits dynamic voltage scaling (DVS) and dynamic power management (DPM) is employed for the spare unit. The framework which is used in the primary unit is composed of a feedback system to follow up workload along with a three-layer yet light-weight energy manager which guarantees hard real-time constraints of the system. Moreover, an optimal approach (but not practical) as a margin for the minimum energy... 

Low energy consumption and fault tolerance are often key objectives in the design of real-time embedded systems. However, these objectives are at odds, and there is a trade-off between them. Real-time systems usually use system level energy reduction methods, i.e., dynamic voltage scaling (DVS) and dynamic power management (DPM). Also hard real-time systems often use replication to achieve fault tolerance. In this paper, we investigate the impact of system level energy reduction methods on both the reliability and energy consumption of hard real-time systems which use replication for fault tolerance. In this analysis, we have considered four various existing energy management methods: 1)... 

Two important objectives in wireless sensor networks are reliability and reducing energy consumption. Hence, overcoming energy constraints and utilizing error control schemes such as Automatic Repeat Request (ARQ) and Forward Error Correction (FEC) are necessary to improve the energy efficiency and reliability. However, these two concerns are at odds, so there is a trade-off between them. Considering this point, the impact of various error control schemes on these objectives and the trade-off between them has been considered in Bluetooth networks recently. However, all these works consider ideal assumptions (e.g., perfect error detection) only. This work evaluates the energy-efficiency of... 

One of the most prominent issues in fully adiabatic circuits is the breaking reversibility problem; i.e., non-adiabatic energy dissipation in the last stage adiabatic gates whose outputs are connected to external circuits. In this paper, we show that the breaking reversibility problem can result in significant energy dissipation. Subsequently, we propose an efficient technique to address the breaking reversibility problem, which is applicable to the usual fully adiabatic logic such as 2LAL, SCRL, and RERL. Detailed SPICE simulations are used to evaluate the proposed technique. The experimental results show that the proposed technique can considerably reduce (e.g., about 74% for RERL, 35% for... 

For real-time embedded systems, energy consumption and reliability are two major design concerns. We consider the problem of minimizing the energy consumption of a set of periodic real-time applications when running on a multi-core system while satisfying given reliability targets. Multi-core platforms provide a good capability for task replication in order to achieve given reliability targets. However, careless task replication may lead to significant energy overhead. Therefore, to provide a given reliability level with a reduced energy overhead, the level of replication and also the voltage and frequency assigned to each task should be determined cautiously. The goal of this paper is to... 

Mixed-criticality systems are introduced due to industrial interest to integrate different types of functionalities with varying importance into a common and shared computing platform. Low-energy consumption is vital in mixed-criticality systems due to their ever-increasing computation requirements and the fact that they are mostly supplied with batteries. In case when high-criticality tasks overrun in such systems, low-criticality tasks can be whether ignored or degraded to assure high-criticality tasks timeliness. We propose a novel energy management method (called Stretch), which lowers the energy consumption of mixed-criticality systems with the cost of degrading service level of... 

Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM... 

Compile-time optimizations play an important role in the efficient design of real-time embedded systems. Usually, compile-time optimizations are designed to reduce average-case execution time (ACET). While ACET is a main concern in high-performance computing systems, in real-time embedded systems, concerns are different and worst-case execution time (WCET) is much more important than ACET. Therefore, WCET reduction is more desirable than ACET reduction in many real-time embedded systems. In this article, we propose a compile-time optimization method aimed at reducing WCET in real-time embedded systems. In the proposed method, based on the predicated execution capability of embedded... 

Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling... 

Embedded systems are usually energy constrained. Moreover, in these systems, increased productivity and reduced time to market are essential for product success. To design complex embedded systems while reducing the development time and cost, there is a great tendency to use commercial off-the-shelf ("COTS") devices. At system level, dynamic voltage and frequency scaling (DVFS) is one of the most effective techniques for energy reduction. Nonetheless, many widely used COTS processors either do not have DVFS or apply DVFS only to processor cores. In this paper, an easy-to-implement COTS-based evaluation platform for low-energy embedded systems is presented. To achieve energy saving, DVFS is... 

Allocating the scratchpad memory (SPM) space to tasks is a challenging problem in real-time multicore embedded systems that use shared SPM. Proper SPM space allocation is important, as it considerably influences the application worst-case execution time (WCET), which is of great importance in real-time applications. To address this problem, in this article we present a dynamic SPM reuse scheme, where SPM space can be reused by other tasks during runtime without requiring any static SPM partitioning. Although the proposed scheme is applied dynamically at runtime, the required decision making is fairly complex and hence cannot be performed at runtime. We have developed techniques to perform... 

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults...