Sharif Digital Repository

Owing to wind power inherent characteristics and technical constraints of power systems operation, a considerable amount of wind energy cannot be delivered to load centers and gets curtailed. Transmission congestion together with temporal mismatch between load and available wind power can be accounted as the main reasons for this unpleasant event. This paper aims to concentrate on the wind energy curtailment for which it provides a combinatorial planning model to maximize wind power utilization. Jointly operating the wind power generation system with pumped hydro energy storage (PHES), the planning procedure tries to reach schemes with the minimum level of wind energy curtailment as well as... 

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

This paper proposes two-dimensional directed graphs (or digraphs for short) as a promising alternative to the popular 2D mesh topology for networks-onchip (NoCs). Mesh is the most popular topology for the NoCs, mainly due to its suitability for on-chip implementation and low cost. However, the fact that a digraph offers a lower diameter than its equivalent linear array of equal cost motivated us to evaluate digraphs as the underlying topology of NoCs. This paper introduces a family of NoC topologies based on three well-known digraphs, namely de Bruijn, shuffleexchange, and Kautz. We study topological properties of the proposed topologies. We show that the proposed digraph-based topologies... 

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

In this brief, we present a fine-grained dark silicon architecture to facilitate further integration of transistors in static random access memory-based reconfigurable devices. In the proposed architecture, we present a technique to power off inactive configuration cells in nonutilized or underutilized logic blocks. We also propose a routing circuitry capable of turning off the configuration cells of connection blocks (CBs) and switch boxes (SBs) in the routing fabric. Experimental results carried out on the Microelectronics Center of North Carolina benchmark show that power consumption in configuration cells of lookup tables, CBs, and SBs can, on average, be reduced by 27%, 75%, and 4%,... 

Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require working with decimal numbers while it has been shown that if we convert decimal number to binary ones, this will negatively influence the preciseness required for these applications. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today's digital systems. While the energy consumption of parallel decimal multipliers has not been addressed in previous works, in this paper we present a comparative study of... 

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

We consider a DVS-enabled single-processor firm real-time (FRT) system with Poisson arrival jobs having exponential execution times and generally distributed relative deadlines. The queue size of the system bounds the number of jobs which may be available therein. Further, the processor speed depends on the number of jobs in the system which varies because of the job arrivals, service completions, and dead-line misses. Thus, the processor power consumption, includling both the dynamic and leakage powers, depends on the stochastic nature of the system. More specifically, the instantaneous dynamic power consumption lonely depends on the number of jobs at that moment. However, the instantaneous... 

A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center... 

The growth in number of data centers and its power consumption costs in recent years, along with ever increasing process variation in nanometer technologies emphasizes the need to incorporate variation-aware power reduction strategies in early design stages. Moreover, since the power characteristics of identically manufactured servers vary in the presence of process variation, their position in the data center should be optimally determined. In this paper, we introduce two heuristic variation-aware server placement algorithm based on power characteristic of servers and heat recirculation model of data center. In the next step, we utilize an Integer Linear Programming (ILP) based... 

This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

This paper proposes two-dimensional directed graphs (or digraphs for short) as a promising alternative to the popular 2D mesh topology for networks-onchip (NoCs). Mesh is the most popular topology for the NoCs, mainly due to its suitability for on-chip implementation and low cost. However, the fact that a digraph offers a lower diameter than its equivalent linear array of equal cost motivated us to evaluate digraphs as the underlying topology of NoCs. This paper introduces a family of NoC topologies based on three well-known digraphs, namely de Bruijn, shuffleexchange, and Kautz. We study topological properties of the proposed topologies. We show that the proposed digraph-based topologies... 

The main goals in zinc electrowinning process are decreasing of power consumption and increasing of current efficiency. The purpose of this research was to investigate effect of different alloy compositions used in production of lead-based anodes on the zinc electrowinning process. The anode compositions prepared and examined in this study were binary alloys Pb - (0.5 and 2 %) Ag and quaternary alloys Pb - 0.5 % Ag - 1 % Ca - 2 % Sn, Pb - 0.5 % Ag - 1 % Ca - 1 % Sn - 1 % Sb and Pb - 0.5 % Ag - 1 % Ca - 1 % Sn - 1 % Bi. The electrowinning experiments were conducted using a laboratory-scale apparatus, at a plating time of 4 hours, a current density of 500 to 1000 A/m2, industrial zinc sulfate... 

In this paper, we present a reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented. When a new application starts, the proposed NoC tailors its topology to the application traffic pattern by changing the inter-router connections to some predefined configuration corresponding to the application. It addresses one of the main drawbacks of the existing application-specific NoC optimization methods, i.e., optimization of NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC when several different applications are integrated into a single modern and complex... 

This paper proposes a power-efficient flow-control method to tackle the problem of crosstalk faults in Network-on-Chips (NoCs). The method, called FRR (Flit Reordering/Rotation), combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a flit sequence which produces the lowest number of OD transitions on NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of...