Sharif Digital Repository

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

In this paper, we aim to improve the performance and power metrics of packet-switched network-on-chips (NoCs) and benefits from the scalability and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The proposed method sets up the virtual point-to-point (VIP) connections over one virtual channel (which bypasses the entire router pipeline) at each physical channel of the NoC. We present two schemes for constructing such VIP circuits. In the first scheme, the circuits are constructed for an application based on its task-graph at design time. The second scheme addresses constructing the connections at run-time using a light-weight... 

Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. For power reduction, multiple voltage-frequency levels are successfully applied to 2-D NoCs, but never with a generic approach to 3-D counterparts; in which low heat conductivity of insulator layers makes high dense temperature distribution at layers away from heat sink. In this paper, a thermal-aware methodology for regular 3-D NoCs based on multiple voltage levels is proposed. Given an application task graph, this methodology determines an efficient mapping of tasks onto network tiles, considering inherent... 

The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and digital signature algorithms utilize this operation in their structures. Although much study is performed to realize the EEA in hardware efficiently, research on its reliable implementations needs to be done to achieve fault-immune reliable structures. In this regard, this paper presents a new concurrent error detection (CED) scheme to provide reliability for the aforementioned sensitive and... 

Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and... 

We study the trade-off between throughput and memory footprint of embedded software that is synthesized from acyclic static dataflow (task graph) specifications targeting distributed memory multiprocessors. We identify iteration overlapping as a knob in the synthesis process by which one can trade application throughput for its memory requirement. Given an initial processor assignment and non-overlapped task schedule, we formally present underlying properties of the problem, such as constraints on a valid iteration overlapping, maximum possible throughput, and minimum memory footprint. Moreover, we develop an effective algorithm for generation of a rich set of design points that provide a... 

Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and point-to-point interconnects), throughput, and reliability are among the most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular and reusable structures with regularity of structural pattern. However, since NoCs are resource-limited, determining how to distribute application load over limited on-chip resources (e.g. switches, buffers, virtual channels, and wires) in order to improve the metrics of interest and satisfy... 

Recently, the tradeoff between low energy consumption and high fault-tolerance has attracted a lot of attention as a key issue in the design of real-time systems. Dynamic Voltage Scaling (DVS) is commonly employed as one of the most effective low energy techniques for real-time systems. It has been observed that the use of feedback-based methods can improve the effectiveness of DVS-enabled systems. In this paper, we have investigated reducing the energy consumption of fault-tolerant hard real-time systems using the feedback control theory. Our proposed method makes the system capable of selecting the proper frequency and voltage settings in order to reduce the energy consumption, while... 

Estimating the energy consumption of applications is a key aspect in optimizing embedded systems energy consumption. This paper proposes a simple yet accurate instruction-level energy estimation model for embedded systems. As a case study, the model parameters were determined for a commonly used ARM7TDMI-based microcontroller. The total energy includes the energy consumption of the processor core, Flash memory, memory controller, and SRAM. The model parameters are instructions opcode, number of shift operations, register bank bit flips, instructions weight and their Hamming distance, and different types of memory accesses. Also, the effect of pipeline stalls have been considered. In order to... 

An effective procedure to incorporate kinematic interaction (KI) aspects in seismic analysis of soil-structures systems was presented. In this regard, first, the effect of KI on the structural response was investigated with special focus on the role of rocking component of foundation input motion (FIM). This was performed parametrically for a wide range of selected nondimensional parameters, which well define the introduced simplified soil-structure model. It was observed that ignoring the effect of rocking input motion may introduce errors, which can be on the unsafe side especially for slender structures with large embedment ratios. On the other hand, it was known that introducing the... 

Today's manufacturing enterprises struggle to adopt cost-effective manufacturing systems. Overview of the recent manufacturing enterprises shows that successful global manufacturing enterprises have distributed their manufacturing capabilities over the globe. The successes of global manufacturing enterprises depend upon the entire worldwide integration of their product development processes and manufacturing operations that are distributed over the globe. Distributed manufacturing agents' collaboration and manufacturing data integrity play a major role in global manufacturing enterprises' success. There are number of works, conducted to enable the distributed manufacturing agents to... 

High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable... 

Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories are highly vulnerable to soft errors and as they contain the most frequently used blocks of the program, their errors can easily propagate in system leading to erroneous results. Unlike the instruction cache, an error in the instruction SPM cannot be corrected using only parity bits by invalidating the erroneous line. This study suggests a low-cost mechanism to protect the instruction SPM against soft errors. The main idea underlying the... 

Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs. Such networks have shorter communication hop count, compared to 2D NoCs, and enjoy fast and power efficient TSV wires in vertical links. Unfortunately, the fabrication process of TSV connections has not matured yet, which results in poor vertical links yield. In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links. AFRA is designed to be simple, high performance, and robust. The simplicity is achieved by applying ZXY and XZXY routings in the absence and presence of fault, respectively.... 

Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique... 

The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the... 

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

Programmable hardware is gaining popularity as it can keep pace with growing performance demand in tight power budget, design and test cost, and serious reliability concerns of future multiprocessor embedded systems. Compatible with this trend, Network-on-Chip, as a potential bottleneck of future multi-cores, should also support pro-grammability. Here, we address this issue in design and implementation of routing algorithm for two-dimensional mesh. To this end, we allocate paths based on input traffic pattern and in parallel with customizing routing restriction for deadlock freedom. To achieve this, we propose extended turn model (ETM), a novel parametric deadlock-free routing for 2D meshes... 

Data aggregation is an effective technique which is introduced to save energy by reducing packet transmissions in WSNs. However, it extends the delay at the intermediate nodes, so it can complicate the handling of delayconstrained data in event-critical applications. Besides, the structure-based aggregation as the dominant data gathering approach in WSNs suffers from high maintenance overhead in dynamic scenarios for event-based applications. In this paper, to make aggregation more efficient, we design a novel structure-free Real-time Data AGgregation protocol, RDAG, using a Real-time Data-aware Routing policy and a Judiciously Waiting policy for spatial and temporal convergence of packets....