Sharif Digital Repository

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to “0” is detected as the faulty cell. Furthermore, consideration of generating the active... 

Fault detection is one of the most important tasks in fault tolerant converters. In this paper, a new method is proposed to detect the faulty cell in a cascaded H-bridge multilevel inverter. The detection technique is based on comparison of the output voltage with reference voltage made by using switching control pulses and DC-Link voltage. Because of the simplicity of this method, it is possible to use a single field-programmable gate array (FPGA) to implement this method and inverter control. The simulation and experimental results confirm the effectiveness of the proposed fault detection technique  

Journal-bearings play a significant role in industrial applications and the necessity of condition monitoring with nondestructive tests is increasing. This paper deals a proper fault detection technique based on power spectral density (PSD) of vibration signals in combination with K-Nearest Neighbor and Support Vector Machine (SVM). The frequency domain vibration signals of an internal combustion engine with three journal-bearing conditions were gained, corresponding to, (i) normal, (ii) corrosion and (iii) excessive wear. The features of the PSD values of vibration signals were extracted using statistical and vibration parameters. The extracted features were used as inputs to the KNN and... 

This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition