Sharif Digital Repository

Vehicles are safety-critical Cyber-Physical Systems (CPSs) consisting of hundreds of control units. The Engine Control Unit (ECU) is a fundamental part of a vehicle, and by applying reliability improvement techniques to the ECU, we can prevent catastrophes, performance degradation, and environmental damage. However, like any other CPS, traditional reliability assessment of the cyber and physical parts is insufficient as these parts are tightly coupled. Furthermore, the ECU consists of many mutually dependent subsystems, the failure of which will fail the whole vehicle system. Hence, to compensate for the hardware redundancy cost, we have improved the reliability of the system's bottleneck.... 

One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

Dependability assessment is an important preliminary in the design of dependable systems. Simulation Based Fault Injection (SBFI) is a common way to evaluate system dependability. To achieve high accuracy in SBFI, a large amount number of fault injection is required, which is very time consuming. Many of ideas are implied to solve this disadvantage of SBFI. In this work, we propose a method that uses information of workload execution on the processor to reduce faults to be injected during the SBFI campaign. We concentrate on Single Event Upsets because of its majority and repeating interval. Our proposed method first gathers information about various regions of the processor by probing... 

Many embedded processors are used in harsh environments and their behavior should be investigated against the incidence of common faults. Fault Injection is a prevalent method to do this investigation. Simulation-based fault injection is one of the most prominent forms of fault injection. A fault model is required to do simulation-based fault injection. Simulated faults should have the most similarity to the real faults. Temperature variation and in the extreme case thermal shock is one of the probable faults in harsh environment. In this thesis, we want to propose fault models for thermal shock in various abstraction levels, evaluate and compare these fault models and present methods to use... 

Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of... 

Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular...