Search for: fault-injection
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    Workload-aware Fault-injection for Speeding-up Evaluation of the Dependable Systems

    , M.Sc. Thesis Sharif University of Technology Javani Jananlu, Saeid (Author) ; Miremadi, Ghassem (Supervisor)
    Dependability assessment is an important preliminary in the design of dependable systems. Simulation Based Fault Injection (SBFI) is a common way to evaluate system dependability. To achieve high accuracy in SBFI, a large amount number of fault injection is required, which is very time consuming. Many of ideas are implied to solve this disadvantage of SBFI. In this work, we propose a method that uses information of workload execution on the processor to reduce faults to be injected during the SBFI campaign. We concentrate on Single Event Upsets because of its majority and repeating interval. Our proposed method first gathers information about various regions of the processor by probing... 

    FPGA-based Fault Injection for Evaluating the Fault Tolerance of Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Mohammadi, Abbas (Author) ; Ejlali, Alireza (Supervisor)
    One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

    Design and Evaluation of a Master/Checker Method for an Embedded Processor

    , M.Sc. Thesis Sharif University of Technology Ebrahimi, Mojtaba (Author) ; Miremadi, Ghasem (Supervisor)
    Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

    Fault Modeling of Transient Faults in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tajik, Hossein (Author) ; Ejlali, Alireza (Supervisor)
    Many embedded processors are used in harsh environments and their behavior should be investigated against the incidence of common faults. Fault Injection is a prevalent method to do this investigation. Simulation-based fault injection is one of the most prominent forms of fault injection. A fault model is required to do simulation-based fault injection. Simulated faults should have the most similarity to the real faults. Temperature variation and in the extreme case thermal shock is one of the probable faults in harsh environment. In this thesis, we want to propose fault models for thermal shock in various abstraction levels, evaluate and compare these fault models and present methods to use... 

    Improving the Reliability of Engine Control Units in Vehicles

    , M.Sc. Thesis Sharif University of Technology Moloudi, Mohammad Amin (Author) ; Ejlali, Alireza (Supervisor)
    Vehicles are safety-critical Cyber-Physical Systems (CPSs) consisting of hundreds of control units. The Engine Control Unit (ECU) is a fundamental part of a vehicle, and by applying reliability improvement techniques to the ECU, we can prevent catastrophes, performance degradation, and environmental damage. However, like any other CPS, traditional reliability assessment of the cyber and physical parts is insufficient as these parts are tightly coupled. Furthermore, the ECU consists of many mutually dependent subsystems, the failure of which will fail the whole vehicle system. Hence, to compensate for the hardware redundancy cost, we have improved the reliability of the system's bottleneck.... 

    Evaluation of Fault Tolerance for SRAM-Based FPGAs by Fault Injection into Configuration Bits

    , M.Sc. Thesis Sharif University of Technology Abolhassani Ghazaani, Elyas (Author) ; Miremadi, Ghasem (Supervisor)
    Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of... 

    RI-COTS: trading performance for reliability improvements in commercial of the shelf systems

    , Article 19th International Symposium on Computer Architecture and Digital Systems, CADS 2017, 21 December 2017 through 22 December 2017 ; Volume 2018-January , March , 2018 , Pages 1-6 ; 9781538643792 (ISBN) Ghasemi, G ; Hosseini Monazzah, A. M ; Farbeh, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    The flexibility of software-based fault tolerant approaches in providing the required level of reliability Commer-cial-Off-The Shelf (COTS) devices made them the first choice in designing safety-critical systems. In this paper, we propose a reliability improvement method for COTS-based systems, so-called, RI-COTS. The main idea behind RI-COTS is to establish a tradeoff between reliability and performance of COTS system through controlling redundant execution at instruction level. RI-COTS is implemented on LEON2 processor VHDL model. Our simulation results show that comparing with the most related studies, RI-COTS can improve the fault detection capability by 20% with only 4% performance... 

    Dependability analysis of data storage systems in presence of soft errors

    , Article IEEE Transactions on Reliability ; Volume 68, Issue 1 , 2019 , Pages 201-215 ; 00189529 (ISSN) Kishani, M ; Tahoori, M ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    In recent years, high availability and reliability of data storage systems (DSS) have been significantly threatened by soft errors occurring in storage controllers. Due to their specific functionality and hardware-software stack, error propagation and manifestation in DSS is quite different from general-purpose computing architectures. To the best of our knowledge, no previous study has examined the system-level effects of soft errors on the availability and reliability of DSS. In this paper, we first analyze the effects of soft errors occurring in the server processors of storage controllers on the entire storage system dependability. To this end, we implement the major functions of a... 

    Evaluation of babbling idiot failures in FlexRay-based networkes

    , Article IFAC Proceedings Volumes (IFAC-PapersOnline) ; Volume 7, Issue PART 1 , 2007 , Pages 399-406 ; 14746670 (ISSN); 9783902661340 (ISBN) Lari, V ; Dehbashi, M ; Miremadi, S. G ; Amiri, M ; Sharif University of Technology
    IFAC Secretariat  2007
    This paper evaluates the error propagation and its effects in babbling idiot failure in a FlexRay-based network. The evaluation is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of four nodes. Nodes in this experiment are considered in two forms: 1) node without bus guardian, 2) node with bus guardian. The results of fault injection show that in first form about 4.57% of faults lead to the babbling idiot failures. Also in second form about 0.75% faults lead... 

    A comprehensive analysis on the resilience of adiabatic logic families against transient faults

    , Article Integration ; Volume 72 , May , 2020 , Pages 183-193 Narimani, R ; Safaei, B ; Ejlali, A ; Sharif University of Technology
    Elsevier B.V  2020
    With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of... 

    A fast, flexible, and easy-to-develop FPGA-based fault injection technique

    , Article Microelectronics Reliability ; Volume 54, Issue 5 , May , 2014 , Pages 1000-1008 ; ISSN: 00262714 Ebrahimi, M ; Mohammadi, A ; Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities... 

    Developing inherently resilient software against soft-errors based on algorithm level inherent features

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Vol. 30, issue. 2 , 2014 , p. 193-212 Arasteh, B ; Miremadi, S. G ; Rahmani, A. M ; Sharif University of Technology
    A potential peculiarity of software systems is that a large number of soft-errors are inherently derated (masked) at the software level. The rate of error-deration may depend on the type of algorithms and data structures used in the software. This paper investigates the effects of the underlying algorithms of programs on the rate of error-deration. Eight different benchmark programs were used in the study; each of them was implemented by four different algorithms, i.e. divide-and-conquer, dynamic, backtracking and branch-and-bound. About 10,000 errors were injected into each program in order to quantify and analyze the error-derating capabilities of different algorithm-designing- techniques.... 

    A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs

    , Article FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology ; 2013 , Pages 398-401 ; 9781479921990 (ISBN) Ghazaani, E. A ; Ghaderi, Z ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes a full-featured fault injection framework to assess reliability of FPGA-based designs. The framework provides non-intrusiveness, portability, flexibility and performance in reliability evaluation of FPGA-based designs against adverse effects of SEUs. It works in a non-intrusive manner, allowing the reliability of ready-to-be-released designs to be assessed independently, without any intrusion into their place and route characteristics. We have studied implications of framework's intrusiveness into design under test by comparing proposed non-intrusive framework with previous intrusive methods; up to 5% deviation in the number of effective faults is observed in intrusive... 

    An efficient technique to tolerate MBU faults in register file of embedded processors

    , Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 115-120 ; 9781467314824 (ISBN) Abazari, M. A ; Fazeli, M ; Patooghy, A ; Miremadi, S. G ; Sharif University of Technology
    This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file... 

    Efficient algorithms to accurately compute derating factors of digital circuits

    , Article Microelectronics Reliability ; Volume 52, Issue 6 , June , 2012 , Pages 1215-1226 ; 00262714 (ISSN) Asadi, H ; Tahoori, M. B ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single... 

    SCFIT: A FPGA-based fault injection technique for SEU fault model

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2012 , Pages 586-589 ; 15301591 (ISSN) ; 9783981080186 (ISBN) Mohammadi, A ; Ebrahimi, M ; Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

    Low cost concurrent error detection for on-chip memory based embedded processors

    , Article Proceedings - 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, 24 October 2011 through 26 October 2011 ; October , 2011 , Pages 114-119 ; 9780769545523 (ISBN) Khosravi, F ; Farbeh, H ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than... 

    A low cost circuit level fault detection technique to full adder design

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) Mozafari, S. H ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition  

    A multi-bit error tolerant register file for a high reliable embedded processor

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 22011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 532-537 ; 9781457718458 (ISBN) Esmaeeli, S ; Hosseini, M ; Vahdat, B. V ; Rashidian, B ; Sharif University of Technology
    The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the... 

    ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 289-292 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Ebrahimi, M ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and...