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Total 45 records

    Fault Modeling of Transient Faults in Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Tajik, Hossein (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    Many embedded processors are used in harsh environments and their behavior should be investigated against the incidence of common faults. Fault Injection is a prevalent method to do this investigation. Simulation-based fault injection is one of the most prominent forms of fault injection. A fault model is required to do simulation-based fault injection. Simulated faults should have the most similarity to the real faults. Temperature variation and in the extreme case thermal shock is one of the probable faults in harsh environment. In this thesis, we want to propose fault models for thermal shock in various abstraction levels, evaluate and compare these fault models and present methods to use... 

    Design and Evaluation of a Master/Checker Method for an Embedded Processor

    , M.Sc. Thesis Sharif University of Technology Ebrahimi, Mojtaba (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract
    Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

    FPGA-based Fault Injection for Evaluating the Fault Tolerance of Embedded Processors

    , M.Sc. Thesis Sharif University of Technology Mohammadi, Abbas (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a... 

    Workload-aware Fault-injection for Speeding-up Evaluation of the Dependable Systems

    , M.Sc. Thesis Sharif University of Technology Javani Jananlu, Saeid (Author) ; Miremadi, Ghassem (Supervisor)
    Abstract
    Dependability assessment is an important preliminary in the design of dependable systems. Simulation Based Fault Injection (SBFI) is a common way to evaluate system dependability. To achieve high accuracy in SBFI, a large amount number of fault injection is required, which is very time consuming. Many of ideas are implied to solve this disadvantage of SBFI. In this work, we propose a method that uses information of workload execution on the processor to reduce faults to be injected during the SBFI campaign. We concentrate on Single Event Upsets because of its majority and repeating interval. Our proposed method first gathers information about various regions of the processor by probing... 

    Improving the Reliability of Engine Control Units in Vehicles

    , M.Sc. Thesis Sharif University of Technology Moloudi, Mohammad Amin (Author) ; Ejlali, Alireza (Supervisor)
    Abstract
    Vehicles are safety-critical Cyber-Physical Systems (CPSs) consisting of hundreds of control units. The Engine Control Unit (ECU) is a fundamental part of a vehicle, and by applying reliability improvement techniques to the ECU, we can prevent catastrophes, performance degradation, and environmental damage. However, like any other CPS, traditional reliability assessment of the cyber and physical parts is insufficient as these parts are tightly coupled. Furthermore, the ECU consists of many mutually dependent subsystems, the failure of which will fail the whole vehicle system. Hence, to compensate for the hardware redundancy cost, we have improved the reliability of the system's bottleneck.... 

    Evaluation of Fault Tolerance for SRAM-Based FPGAs by Fault Injection into Configuration Bits

    , M.Sc. Thesis Sharif University of Technology Abolhassani Ghazaani, Elyas (Author) ; Miremadi, Ghasem (Supervisor)
    Abstract
    Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of... 

    Transient error detection in embedded systems using reconfigurable components

    , Article Industrial Embedded Systems - IES'2006, Antibes Juan-Les-Pins, 18 October 2006 through 20 October 2006 ; 2006 ; 142440777X (ISBN); 9781424407774 (ISBN) Vahdatpour, A ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    2006
    Abstract
    In this paper, a hardware control flow checking technique is presented and evaluated. This technique uses reconfigurable of the shelf FPGA in order to concurrently check the execution flow of the target micro processor. The technique assigns signatures to the main program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. The main characteristic of this technique is its ability to be applied to any kind of processor architecture and platforms. The low imposed hardware and performance overhead by this technique makes it suitable for those applications in which cost is a major concern, such as... 

    System-level vulnerability estimation for data caches

    , Article 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, 13 December 2010 through 15 December 2010 ; 2010 , Pages 157-164 ; 9780769542898 (ISBN) Haghdoost, A ; Asadi, H ; Baniasadi, A ; Sharif University of Technology
    2010
    Abstract
    Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In... 

    Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 70-75 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Fazeli, M ; Ahmadian, S. N ; Miremadi, S. G ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    2011
    Abstract
    In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and... 

    Soft error modeling and remediation techniques in ASIC designs

    , Article Microelectronics Journal ; Volume 41, Issue 8 , August , 2010 , Pages 506-522 ; 00262692 (ISSN) Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    2010
    Abstract
    Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain... 

    ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 289-292 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Ebrahimi, M ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    2011
    Abstract
    We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and... 

    SCFIT: A FPGA-based fault injection technique for SEU fault model

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2012 , Pages 586-589 ; 15301591 (ISSN) ; 9783981080186 (ISBN) Mohammadi, A ; Ebrahimi, M ; Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    2012
    Abstract
    In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection  

    RI-COTS: trading performance for reliability improvements in commercial of the shelf systems

    , Article 19th International Symposium on Computer Architecture and Digital Systems, CADS 2017, 21 December 2017 through 22 December 2017 ; Volume 2018-January , March , 2018 , Pages 1-6 ; 9781538643792 (ISBN) Ghasemi, G ; Hosseini Monazzah, A. M ; Farbeh, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    The flexibility of software-based fault tolerant approaches in providing the required level of reliability Commer-cial-Off-The Shelf (COTS) devices made them the first choice in designing safety-critical systems. In this paper, we propose a reliability improvement method for COTS-based systems, so-called, RI-COTS. The main idea behind RI-COTS is to establish a tradeoff between reliability and performance of COTS system through controlling redundant execution at instruction level. RI-COTS is implemented on LEON2 processor VHDL model. Our simulation results show that comparing with the most related studies, RI-COTS can improve the fault detection capability by 20% with only 4% performance... 

    Low cost concurrent error detection for on-chip memory based embedded processors

    , Article Proceedings - 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, 24 October 2011 through 26 October 2011 ; October , 2011 , Pages 114-119 ; 9780769545523 (ISBN) Khosravi, F ; Farbeh, H ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    Abstract
    This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than... 

    Investigation and reduction of fault sensitivity in the FlexRay communication controller registers

    , Article 27th International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2008, Newcastle upon Tyne, 22 September 2008 through 25 September 2008 ; Volume 5219 LNCS , 2008 , Pages 153-166 ; 03029743 (ISSN); 3540876979 (ISBN); 9783540876977 (ISBN) Sedaghat, Y ; Miremadi, S. G ; Sharif University of Technology
    2008
    Abstract
    It is now widely believed that FlexRay communication protocol will become the de-facto standard for distributed safety-critical automotive systems. In this paper, the fault sensitivity of the FlexRay communication controller registers are investigated using transient single bit-flip fault injection. To do this, a FlexRay bus network, composed of four nodes, was modeled. A total of 135,600 transient single bit-flip faults were injected to all 408 accessible single-bit and multiple-bit registers of the communication controller in one node. The results showed that among all 408 accessible registers, 30 registers were immediately affected by the injected faults. The results also showed that... 

    FPGA-based fault injection into synthesizable verilog HDL models

    , Article 2nd IEEE International Conference on Secure System Integration and Reliability Improvement, SSIRI 2008, Yokohama, 14 July 2008 through 17 July 2008 ; 2008 , Pages 143-149 ; 9780769532660 (ISBN) Shokrolah Shirazi, M ; Miremadi, S. G ; Sharif University of Technology
    2008
    Abstract
    This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good controllability and observability. As a case study, an OpenRISC 1200 microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient, and SEU faults were injected into this microprocessor. The results show that the FITO tool is more than 79 times faster than a pure simulation-based fault injection with only 2.5% FPGA area overhead. © 2008 IEEE  

    Feature specific control flow checking in COTS-based embedded systems

    , Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 58-63 ; 9780769540900 (ISBN) Rajabzadeh, A ; Miremadi, S.G ; IARIA ; Sharif University of Technology
    2010
    Abstract
    While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

    Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A

    , Article Proceedings of the IEEE International Workshop on Behavioral Modeling and Simulation, BMAS, 23 September 2010 through 24 September 2010, San Jose, CA ; September , 2010 , Pages 69-74 ; 21603804 (ISSN) ; 9781424489954 (ISBN) Ahmadian, S. N ; Miremadi, S. G ; Sharif University of Technology
    2010
    Abstract
    Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported  

    Fault effects in FlexRay-based networks with hybrid topology

    , Article ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings, 4 March 2008 through 7 March 2008, Barcelona ; 2008 , Pages 491-496 ; 0769531024 (ISBN); 9780769531021 (ISBN) Dehbashi, M ; Lari, V ; Miremadi, S. G ; Shokrollah Shirazi, M ; Sharif University of Technology
    2008
    Abstract
    This paper investigates fault effects and error propagation in a FlexRay-based network with hybrid topology that includes a bus subnetwork and a star subnetwork "The investigation is based on about 43500 bit-flip fault injection inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of eight nodes (four nodes in the bus subnetwork and four nodes in the star subnetwork). The faults are injected in a node of the bus subnetwork and a node of the star subnetwork of the hybrid network. Then, the faults resulting in... 

    Experimental evaluation of three concurrent error detection mechanisms

    , Article 2006 International Conference on Microelectronics, ICM 2006, Dhahran, 16 December 2006 through 19 December 2006 ; 2006 , Pages 67-70 ; 1424407656 (ISBN); 9781424407651 (ISBN) Vahdatpour, A ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    2006
    Abstract
    This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental...