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field-programmable-gate-array--fpga
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Digital Design and Implementation of a Multilevel OCDMA System
, M.Sc. Thesis Sharif University of Technology ; Salehi, Javad (Supervisor)
Abstract
Optical Wireless Communication is believed to have a great potential in establishing point to point connection and have attracted an unexpected growth in research , applications and market. Furthermore, Optical wireless systems have recently emerged as a new means of communication, especially in places where electromagnetic interferences is of utmost concern such as in passenger planes and hospitals and in other communications applications where cost could is of concern. In this thesis we build upon previously introduced wireless optical code-division multiple –access communication. In the context of an OCDMA system we begin our study by considering synchronization circuit via a...
Design of FPGA Cluster Platform For Cryptanalysis Applications
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Daily improvements in technology and exchanging important information via internet and connection networks make data and connection security a significant problem. Cryptology is the branch of knowledge which concerns secret communications in all of its aspects. Two major areas of cryptology are cryptography and cryptanalysis. Cryptography is a branch of cryptology concerned with protecting communications from being read by unauthorized people.
Cryptologists design and create algorithms to improve cryptography along with finding methods to crack those algorithms. Cryptanalysis is a branch of cryptology concerned with cracking the cryptographic systems used by others.
Cryptographic...
Cryptologists design and create algorithms to improve cryptography along with finding methods to crack those algorithms. Cryptanalysis is a branch of cryptology concerned with cracking the cryptographic systems used by others.
Cryptographic...
Implementation of the Digital Part of DVB-T Protocol with Reduced Power and Area
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shaahin (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
Abstract
An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for...
Analysis, Design and Implementation of a Low Power and High Speed Sound Source Localizer
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor) ; Gholampour, Iman (Supervisor)
Abstract
Throughout localization algorithms, sound source localization has received much interest using microphone array. Applications like tracking and determining angle of acoustic signal arrival have been combined with array processing techniques in the previous decade. Distributed micro sensor array have been suggested for a wide range of nowaday’s localization algorithms. The major goals are monitoring the environment, distinction, and pursue some phenomenon. This type of networks can be utilized for military application in tracking acoustic sources. Today’s advancement in technology allows implementation of the ultra low cost and low power integrated circuit for such application in the form of...
Reconfigurable Architecture For Cryptanalysis Applications
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Nowadays, the significance of securing data and information is undeniable. Cryptography is being used to provide data security. In addition, cryptanalysis is required to evaluate the effectiveness of cryptography methods, and hence, it is an essential concept for securing data. In general, the cryptography functions shall be designed in a way to impose a high load of time-intensive operations to prevent an adversary from accessing the main data from the encrypted data. As a result, cryptography and cryptanalysis algorithms need high performance computations. So far, a number of methods have been proposed to support the required performance. These methods include: distributed computing and...
Accelerated FPGA-Based NOC Simulation With Software Configuration
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
To address these challenges, we propose a new...
To address these challenges, we propose a new...
High Speed Digital Receiver, Design and Implementation
, M.Sc. Thesis Sharif University of Technology ; Sanaei, Esmaeel (Supervisor) ; Pezeshk, Amir Mansoor (Supervisor)
Abstract
Nowadays, increasingly improvements in the digital technology and the advantages of using digital signal processing methods lead engineers to use digital signal processing instead of analog processing in variant domains. However, speed limitations in analog to digital converters (ADCs) and data transfer ports prevent its penetration to high frequency signals region. In this thesis, an Instantaneous Frequency Measurement (IFM) system that can measure frequency in the range of 2-18 GHz is implemented fully digital (DIFM) on FPGA. To do so, monobit sampling technique with the sampling rate of 10 GHz is selected, and GTX high speed serial port is configured to transfer digital data into FPGA....
Design and Simulation of Dust Control System in the Air with the FPGA
, M.Sc. Thesis Sharif University of Technology ; Vosoughi Vahdat, Bijan (Supervisor) ; Hashemi, Matin (Co-Advisor)Improving Energy Efficiency in Multi-processor Soft-Core Systems Using System-level Techniques
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
The ever increasing density and performance of FPGAs, has increased the importance and popularity of soft processors. One major research concern in this regard lays in the field of energy efficiency of the system on FPGA. This work is particularly focused on the energy efficiency of multiprocessor structures on FPGA using system level techniques. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy, i.e. caches. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this thesis, two novel cache architecture, primarily aimed at...
Design and Implementation of 2.5 Gbps Circuit Switching Fabric
, M.Sc. Thesis Sharif University of Technology ; Pakravan, Mohammad Reza (Supervisor) ; Movahhedy, Mohammad Reza (Supervisor)
Abstract
Providing high bandwidth network infrastructures for ever increasing need of data transport is of great importance. The underling infrastructure for many communication services such as GSM/3G/4G mobile networks and Internet services is Synchronous Digital Hierarchy (SDH) optical transport systems. SDH are standardized protocols that multiplex multiple lower rate digital bit streams, such as E1 and Ethernet, and transfer them synchronously over optical fiber using lasers or LEDs. In addition to high data transfer rates, flexible network management and protection mechanisms have great importance, hence are part of SDH standards. In order to obtain flexible network architecture and protected...
Exploiting Bandpass Sampling and Compressed Sensing Alghorithms for RF to Digital Direct Conversion
, M.Sc. Thesis Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor) ; Pezeshk, Amir Mansour (Co-Advisor)
Abstract
The target of reconnaissance receivers is to detect radio frequencies and pulses present in the environment and extracting their characteristics. To receive the signals in the range of 2 to 18 GHz, different receptors can be used. Each receptor has its specific aplications, advantages and disadvantages. In this project, we proposed a receptor scheme with the following features: 1-simple hardware, 2-ability to detect simultaneous signals, 3-hundred percent probability of intercept (POI), 4-high input bandwidth and 5-rapid threat detection. To have such a receptor, we should move data processing parts of receptor to digital domain as much as possible, and reduce the amount of analog...
Managing Shared Use of an FPGA-based Accelerator among Virtual Machines
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Using accelerators inside high speed servers can reduce execution time of applications and total power usage of the system. Sharing accelerator between virtual machines of a server decrease both cost and power, however it won’t provide the gained speedup of using dedicated accelerator for each virtual machines. Creation of an appropriate set of accelerators required for virtual machines, management of accesses to the accelerator, prioritizing and scheduling of requests and reconfiguration type of accelerator are the most important challenges that this project has been dealt with. The main objective of this project is implementing the necessary infrastructure to share an FPGA-based...
System Level Modeling and Optimization of Accelerator-CPU Communication in Data Centers
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Due to the data centers rapid growth and introduction of a new basic type of massive data processing platforms which requires accelerators to speedup computation and enhance the efficiency and reduce power consumption, using accelerators is inevitable. Communication and data transfer time between software and hardware is the most of time spent on the use of accelerators. By optimizing this part of the hardware / software platform, we have achieved substantial results in this area. The aim of our study is to organize a survey of real accelerator characteristics. To figure out its defects and main drawbacks, in addition to improving the overall efficiency of system. The implementation of...
Design and Implementation Real-Time Simulator for CHB Converter using FPGA
, M.Sc. Thesis Sharif University of Technology ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
With development of power electronic science and with the existence of different power electronic converters in this field, the need for improving their operation and the fault detection methods of these converters, the need for simulation and test of them is strong felt. However, experimental constrain such as damage risks, reliability, costs, and so on obviate the need for making the converter and the need for testing it and its controller. Accordingly, we do the testing on a special platform for Real-Time simulation.Control/protection platform needs to be tested and its functionality should be verified prior to installation and commissioning.Testing in theReal-Time simulator environment...
Secure Implementation of Cryptographic Algorithms on FPGA
, M.Sc. Thesis Sharif University of Technology ; Bayat-Sarmadi, Siavash (Supervisor)
Abstract
Security of cryptographic devices lies amongst the most important issues in the field of hardware security. It is frequently seen that in the process of designing cryptographic systems insufficient attention is paid to the physical implementation details. This is happening while a lot of secret information is known to be leaked through side-channels such as power consumption, electromagnetic emission and execution time. Side-channel attacks are able to reveal secret keys by using these side-channel leakages. Additionally, side-channel attacks are one of the most powerful but low-cost attacks that put the security of cryptographic systems in vain. It can be claimed that the most dangerous...
A Power-efficient Architecture for SRAM-based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
Significant increase of static power with downscaling of transistor feature size and threshold voltage has lead to the end of Dennard scaling. This obstacle has put a Power Wall to further integration of CMOS technology in Field Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is to apply power gating to the inactive fractions of a single die, referred to as Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs) which suffer from poor logic utilization, and subsequently, limiting the benefits of power gating techniques. This thesis proposes a heterogeneous Power-Efficient...
Design and Implementation of FPGA Based Real Time Simulator for Power Electronic Converters
, M.Sc. Thesis Sharif University of Technology ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
Real-time Simulator plays an important role in the test of power electronic converters. Using of this simulators and Hardware-in-the-loop tests, cost and time of experiments will redused, furthermore those experiments which are not operative on the real system, can be achived. However, the accuracy of the used model in simulation as well as fast and easy programming of these simulators is very important. Therefore in this thesis, design and implementation of real-time simulator for power electronic converters have been discussed that in addition to high accuracy of the simulation, implementation of the several tests will be easy. As regards the power electronic switch is the most important...
A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration
, M.Sc. Thesis Sharif University of Technology ; Bayat-Sarmadi, Siavash (Supervisor)
Abstract
Hardware Trojans have emerged as a major concern for integrated circuits in recent years. As a result, detecting Trojans has become an important issue in critical applications, such as finance and health. In this work, a trusted platform for detecting Trojans in FPGA bitstreams is presented. The proposed methodology takes advantage of increased Trojan activation, caused by transition aware partitioning of the circuit, while it benefits partial reconfiguration feature of FPGAs to reduce area overhead. Simulation results, performed for the transition probability thresholds of 〖10〗^(-4) and 〖2×10〗^(-5), show that this method increases the ratio of the number of transitions in the Trojan...
RF Signal Sampling using Compress Sensing and its Implementation on FPGA
, M.Sc. Thesis Sharif University of Technology ; Pezeshk, Amir Mansour (Supervisor)
Abstract
Analog-to-digital conversion and signal processing has been increasing due to its many advantages. So that mostly we prefer to convert signal from analog area to digital samples, then they are processed and finaly put the result signal at the system output. How ever because the restriction of the sampling rate, Prevent the spread of digital processing for the high-frequency signal (RF). In recent years, ADCs sampling rate rise up to several GHz (for example ADC with 4 GSPS and 12 bits for TI) that output of the these ADCs by powerful and fast FPGAs are processed but According to Shannon theorem band width of these ADCs is not desirable.the goal of this thesis uses of the compressed sensing...
Design of a Fault Tolerant SPARC Based Micro Processor On FPGA
, M.Sc. Thesis Sharif University of Technology ; Rashidian, Bijan (Supervisor) ; Vosoughi Vahdat, Bijan (Supervisor)
Abstract
In this thesis, LEON Processor was chosen for its compatible architecture that can be implemented on a wide range of FPGAs. The final designed processor is aimed to conquer soft and hard errors that occur due to cosmic radiations in SRAM cells of an FPGA. The system can finally resist all single SEUs that happen in flip flops and all 4 random errors that take place in each register of the register file. All the flip flops and latches are protected using a TMR scheme. The information redundancy in the regiester file to overcome all 4 random errors is 168% and the errors are corrected by means of a mechanesim that is masked from the processor core. In cache memory, each 32 bit data is...