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field-programmable-gate-arrays--fpga
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Evaluating the Energy Consumption of Fault-Tolerance Mechanisms In Processors Implemented on Sram-Based Fpgas
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. The soft errors vulnerability of SRAM-based FPGAs limits their usage in safety-critical applications. Moreover, the rate of multiple soft errors increases due to the feature size reduction. Hence, this issue becomes a challenge against reliability of the implemented circuit on SRAM-based FPGAs. Appealing to specifics such as low cost and re-configurability in SRAM based FPGAs provide this ability to change implemented design remotely. This advantage is not negligible in safety critical...
Design of A Digitally Controlled Bias Chip For A Transceiver
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Sheikhaei, Samad (Supervisor)
Abstract
Advances in IC fabrication makes possible have systems on chips. In this thesis we have designed and fabricated a digitally controlled bias chip for a transceiver which can be programmed by its digital interface. In this thesis, briefly we review basics of voltage regulators and methods for controlling them. Then we introduce high voltage 0.18um CMOS technology. In this thesis, we describe the requirements of a specific transceiver and present a system to overcome these requirements. This system has positive, negative and internal regulators, a five-bit analog to digital converter, temperature sensors, power amplifier controller and digital serial interface. In this thesis, we present a...
A Dependable Routing Architecture for Reconfigurable Devices
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
Reconfigurable devices are a popular platform for fast prototyping of digital system due to having high performance of hardware implementation along with flexibility of software. However, reconfigurable devices suffer from area, performance and dependability gaps in comparison with their Application Specific Integrated Circuit (ASIC) counterparts, which greatly limits their application.
The dependability gap originates from the sensitivty of configuration memory to soft errors. When a reconfigurable device configuration memory is affected by soft errors, their configuration will be invalid until reconfigured. Since the routing fabric is the origion of over 80% of soft errors in...
The dependability gap originates from the sensitivty of configuration memory to soft errors. When a reconfigurable device configuration memory is affected by soft errors, their configuration will be invalid until reconfigured. Since the routing fabric is the origion of over 80% of soft errors in...
Accelerating Big Data Stream Processing by FPGA-implementation of Parts of the Topology Graph
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
In recent years, big data processing plays an important role in the era of information technology. The exponential growth of big data volume increases the need for data centers and infrastructures with more processing power. Due to dark silicon and scalability limitations in deep-submicron, the increasing trend of server performance slows down. Therefore, hardware accelerators such as FPGA and GPU are become increasingly popular for improvement of data center processing power. There are two types of big data processing based on the application: stream processing and batch processing. With the widespread use of social networks, online control systems and internet of things services, the...
An RT-Level Low Power Design Technique for Digital Circuits Implemented on FPGAs
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
RT-level techniques are one of the most important categories of techniques employed for decreasing power consumption in digital systems. These techniques are usually applied in the HDL description of the system, however some of them are applicable automatically by the synthesis tools. Some of the most commonly used RT-level techniques include Operand isolation, Clock gating, Concurrency & Redundancy, Pre-computation and Pipeline for low power. However these techniques have been mostly employed in ASIC designs, and FPGAs have scarcely been addressed. Application of these techniques on FPGAs might need special considerations, since resources on FPGAs are inherently different than their ASIC...
Improving Resolution in Millimeter-Wave Imaging Systems
, M.Sc. Thesis Sharif University of Technology ; Shabany, Mahdi (Supervisor) ; Kavehvash, Zahra ($item.subfieldsMap.e)
Abstract
Nowadays, millimeter-wave imaging is widely used in security and medical applications. The growing threat from terrorist attacks is driven research on novel ways to enhance security inspection systems. Millimeter-wave imaging not only is an effective option of penetrating into dielectric materials including cloth, but also provides suitable imaging resolution. Moreover, millimeter-wave imaging is capable of identifying different materials making it a promising option for concealed weapon detection. In spite of X-ray, millimeter-wave imaging is non-ionizing, allowing for non-invasive imaging. In this thesis, first we investigate different millimeter-wave imaging systems and reconstruction...
Low-cost, Non-infrared, MRI-compatible Eye Tracker for Research
, M.Sc. Thesis Sharif University of Technology ; Ghazizadeh, Ali (Supervisor)
Abstract
Looking for eye paths is widely used in various research and even commercial areas, Eye trackers that are used commercially today do this by using infrared transmitters and receivers. As the speed and performance of the processors advanced, many efforts have been made to create an eye-tracking device using visible light without any movement restrictions for the subject, and efforts to increase the accuracy and speed of sampling are still ongoing; The initial methods proposed in this area are feature-based, but newer papers and researches have used Deep learning methods to do this. The commonly used methods for eye tracking in visible light are three main steps: 1. Fetching frames from the...
Reconfigurable Architecture For Cryptanalysis Applications
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Nowadays, the significance of securing data and information is undeniable. Cryptography is being used to provide data security. In addition, cryptanalysis is required to evaluate the effectiveness of cryptography methods, and hence, it is an essential concept for securing data. In general, the cryptography functions shall be designed in a way to impose a high load of time-intensive operations to prevent an adversary from accessing the main data from the encrypted data. As a result, cryptography and cryptanalysis algorithms need high performance computations. So far, a number of methods have been proposed to support the required performance. These methods include: distributed computing and...
An Efficient Reconfigurable Architecture to Speed up Machine Learning Algorithms
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
Machine learning algorithms are achieving state-of-the-art performance in many various applications such as image processing, machine vision, speech recognition, diagnosis diseases, robotics, military, and aerospace. For decades, the usage of machine learning algorithms especially Neural Network Algorithms (NNA) has been restricted due to their complexity and high computation time of available inefficient hardwares. Although advances in technology and the emergence of powerful processors has increased the usage of NNAs, especially Deep Neuaral Networks (DNNs), the research gap in machine learning hardware platform with high performance as well as high energy efficiency is still remaining....
Managing Shared Use of an FPGA-based Accelerator among Virtual Machines
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Using accelerators inside high speed servers can reduce execution time of applications and total power usage of the system. Sharing accelerator between virtual machines of a server decrease both cost and power, however it won’t provide the gained speedup of using dedicated accelerator for each virtual machines. Creation of an appropriate set of accelerators required for virtual machines, management of accesses to the accelerator, prioritizing and scheduling of requests and reconfiguration type of accelerator are the most important challenges that this project has been dealt with. The main objective of this project is implementing the necessary infrastructure to share an FPGA-based...
Accelerating Network Firewalls
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
With the proliferation of Internet-based applications and malicious attacks, security has become one of the most influential aspects in the network and, it should be considered from the beginning steps of designing the network infrastructure. Based on the fact that pattern matching is considered as one of the most important roles of security devices or applications, it becomes an important procedure in firewalls that have been classified as security equipments which adopt a security mechanism in order to restrict the traffic exchanged between networks and particular users or certain applications. While the trend of using compressed traffic is drastically increasing, this type of traffic is...
Open-Circuit Fault Detection and Localization in Five-Level Active Neutral Point Clamped Converter
, M.Sc. Thesis Sharif University of Technology ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
Five-Level Active-Neutral-Point -Clamped (5L-ANPC) converter is used for medium-voltage and high-power applications. In many of these applications, availability and robustness against fault are the most important issues. On the other hand, this converter is made of a large number of power semiconductor switches, diodes and capacitors which could increase the failure probability. Thus, fault detection of power circuit elements is necessary for fault tolerant operation of the converter. In this thesis, following an introduction to the topology and operation principles of Five-Level Active Neutral point clamped converter, a novel open-circuit fault detection and localization method is...
Implementation of the Digital Part of DVB-T Protocol with Reduced Power and Area
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shaahin (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
Abstract
An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for...
Accelerated FPGA-Based NOC Simulation With Software Configuration
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
To address these challenges, we propose a new...
To address these challenges, we propose a new...
FPGA-based Fault Injection for Evaluating the Fault Tolerance of Embedded Processors
,
M.Sc. Thesis
Sharif University of Technology
;
Ejlali, Alireza
(Supervisor)
Abstract
One the most important issues in most of embedded systems is reliability and fault tolerance.Ensure of correct operation and evaluate reliability and fault tolerance of embedded proces-sors as a critical part of embedded systems, would be necessary. Fault injection is one themostly used methods for evaluating those features. Using FPGA devices is a good alterna-tive for time consuming simulation-based fault injection method because of their speed. But,there are some critical issues in FPGA-based fault injection methods which are controllabil-ity and observability. In addition to need for efficient and applicable observation and controlmechanism to handle fault injection experiments, a...
VLSI Architecture for Base Band Part of an Optical OFDM Transceiver
, M.Sc. Thesis Sharif University of Technology ; Shabany, Mahdi (Supervisor) ; Salehi, Javad (Supervisor)
Abstract
Optical Communication is a promising technology in access networks because of bandwidth hungry application like videos. So fiber Optic is an important candidate as a media in networks. There are different methods of modulation for transferring data through a channel. Among all, Orthogonal Frequency Division Multiplexing is a method which used in most wired and wireless systems. Recent researches show that OFDM is also a good approach for optical communication.
In this thesis we concentrate on hardware implementation of digital part of an Optical OFDM transceiver. In the first step we ignore the effect of optical channel and design and simulate the transmitter and receiver. After that we...
In this thesis we concentrate on hardware implementation of digital part of an Optical OFDM transceiver. In the first step we ignore the effect of optical channel and design and simulate the transmitter and receiver. After that we...
Design of Fault Tolerant Processor for Implementation on SRAM Based FPGAs
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghasem (Supervisor)
Abstract
Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the...
Secure Implementation of Cryptographic Algorithms on FPGA
, M.Sc. Thesis Sharif University of Technology ; Bayat-Sarmadi, Siavash (Supervisor)
Abstract
Security of cryptographic devices lies amongst the most important issues in the field of hardware security. It is frequently seen that in the process of designing cryptographic systems insufficient attention is paid to the physical implementation details. This is happening while a lot of secret information is known to be leaked through side-channels such as power consumption, electromagnetic emission and execution time. Side-channel attacks are able to reveal secret keys by using these side-channel leakages. Additionally, side-channel attacks are one of the most powerful but low-cost attacks that put the security of cryptographic systems in vain. It can be claimed that the most dangerous...
High-Performance Architecture for Post-Quantum Cryptography Based on Elliptic Curve Isogeny
, Ph.D. Dissertation Sharif University of Technology ; Bayat Sarmadi, Siavash (Supervisor)
Abstract
Public-key cryptography is vital to secure digital communication. The classic instances of these cryptosystems are insecure against large-scale quantum computers. As a result, post-quantum cryptography has emerged as a replacement, which includes different categories. Isogeny-based schemes are one of the promising candidates mainly because of their smaller public key length. Due to high computational cost of such schemes, efficient implementations are significantly important. In this thesis, we have presented various solutions at three different abstraction layers. At the lowest layer, which deals with modular arithmetic, two hardware architectures are presented to perform modular...
FPGA-Based Implementation of Deep Learning Accelerator with Concentration on Intrusion Detection Systems
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Intrusion Detection System (IDS) is an equipment destined to provide computer networks security. In recent years, Machine Learning and Deep Neural Network (DNN) methods have been considered as a way to detect new network attacks. Due to the huge amounts of calculations needed for these methods, there is a need for high performance and parallel or specific processors, such as Application Specific Integrated Circuit (ASIC), Graphical Processor Unit (GPU) and Field-Programmable Gate Array (FPGA). The latter seems more suitable than others due to its higher configurability and lesser power consumption. The goal of this study is the acceleration of a DNN-based IDS on FPGA. In this study, which is...