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field-programmable-gate-arrays--fpga
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Total 167 records
Design of Telecommand Subsystem of a LEO Satellite Based on the FPGA
, M.Sc. Thesis Sharif University of Technology ; Vosoghi, Bijan (Supervisor)
Abstract
Achieving technical knowledge and technology of design, build, test and launch satellites in each country is a strategic issue due to extension of satellite applications in various aspects of human life. One of the most important subsystems of a satellite is the telecommand part. This part is responsible for decode, receive, interpret, and distribution of commands and data received from the ground station. This part in terms of reliability is the most critical part of satellite because it coordinates satellite and ground station and also is the part which should be turned on during the mission and controls other parts of satellite. In other words this part should be design with high...
Designing a 32-Bit Fault-Tolerant ALU Using EDAC
, M.Sc. Thesis Sharif University of Technology ; Vosughi Vahdat, Bijan (Supervisor) ; Mortazavi, Mohammad (Supervisor)
Abstract
Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since...
Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since...
Feasibility Study of TMS (DSP-Core Base)and Xilinx FPGA for Speech Algorithm
, M.Sc. Thesis Sharif University of Technology ; Mortazavi, Mohammad (Supervisor) ; Ghorshi, Mohammad Ali (Supervisor)
Abstract
Digital Signal Processing (DSP) is used in a wide range of applications such as high-definition TV, digital audio, multimedia, digital cameras, radar, sonar detectors, biomedical imaging, global positioning, digital radio, speech recognition and etc. These applications can be implemented by either DSP processors or FPGA technology. Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. These devices have seen a tremendous growth in the last decade, finding use in everything from cellular telephones to advanced scientific instruments. On the other hand, the rise of FPGA in the signal processing realm could be assigned to hardware to...
Digital Design and Implementation of a Multilevel OCDMA System
, M.Sc. Thesis Sharif University of Technology ; Salehi, Javad (Supervisor)
Abstract
Optical Wireless Communication is believed to have a great potential in establishing point to point connection and have attracted an unexpected growth in research , applications and market. Furthermore, Optical wireless systems have recently emerged as a new means of communication, especially in places where electromagnetic interferences is of utmost concern such as in passenger planes and hospitals and in other communications applications where cost could is of concern. In this thesis we build upon previously introduced wireless optical code-division multiple –access communication. In the context of an OCDMA system we begin our study by considering synchronization circuit via a...
Accelerating Network Firewalls
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
With the proliferation of Internet-based applications and malicious attacks, security has become one of the most influential aspects in the network and, it should be considered from the beginning steps of designing the network infrastructure. Based on the fact that pattern matching is considered as one of the most important roles of security devices or applications, it becomes an important procedure in firewalls that have been classified as security equipments which adopt a security mechanism in order to restrict the traffic exchanged between networks and particular users or certain applications. While the trend of using compressed traffic is drastically increasing, this type of traffic is...
Dynamics Identification and Control of Robotic Aerial Vehicles Based on Modeling of DSP and FPGA Integrated Circuits with Emphasis on Multicopters
, M.Sc. Thesis Sharif University of Technology ; Banazadeh, Afshin (Supervisor) ; Pourtakdoust, Hossein (Co-Supervisor)
Abstract
One of the steps toward applying artificial intelligence in the field of unmanned aerial vehicles, as they are extending is the development of the controller unit and expansion of the basis of its implementation. In the beginning, one of the targets of this research is to offer an intelligent controller that utilizes an RBF neural network. Second, in order to physical parameters estimation in case of real-time system identification, an Augmented Extended Kalman Filter (AEKF) has been purposed which is capable of filtering the noise of sensors in addition to estimate some of the physical parameters. Furthermore, to check the generalization ability of the structure, three different cases of...
Accelerating Numerical Solution of Steady and Unsteady Equations Using FPGA
, Ph.D. Dissertation Sharif University of Technology ; Ebrahimi, Abbas (Supervisor)
Abstract
Nowadays one of the main challenges facing fluid dynamics simulations is the long duration of numerical calculations. The goal of this research is to use FPGAs (Field Programmable Gate Arrays) to accelerate fluid dynamics solutions. First, the ability of FPGAs in mathematical operations on floating point numbers is studied. Then, various fluid dynamics problems are implemented on the FPGA hardware, and each one is solved separately. Unsteady 1D Couette problem, 2D potential flow (Laplace equation), incompressible viscous fluid flow over a backward facing step, and compressible inviscid flow over a bump are some of the problems in question. FPGA is an integrated circuit containing a number of...
Protein Interaction Prediction Through Efficient FPGA and GPU Implementation
, M.Sc. Thesis Sharif University of Technology ; Koohi, Somayyeh (Supervisor)
Abstract
Alignment of genetic sequences is a fundamental part of genetic and bio-science. Alignment of DNA and protein sequences has an effective role in accelerating and simplifying problems in Bioinformatics like predicting protein interactions. Smith-Waterman algorithm is a precise algorithm for performing local alignment, suffering from computation complexity. There are some implementations on CPU, GPU, and FPGA platforms in order to reduce the run time of this algorithm. FPGA implementation is considered because of low power consumption and high degree of parallelism. With using pipeline and hardware redundancy techniques, various architectures have been proposed and implemented. In the best...
Hardware Acceleration of Convolutional Neural Networks by Computational Prediction
, M.Sc. Thesis Sharif University of Technology ; Bayatsarmadi, Siavash (Supervisor)
Abstract
Recently, Convolutional neural networks (CNNs) are widely used in many artificial intelligence applications such as image processing, speech processing and robotics. The neural networks superior accuracy comes at the cost of high computational complexity. Recent studies show that these operations can be performed in parallel. Therefore, as graphic processing units (GPUs) offer the best performance in terms of computational power and throughput, they are widely used to implement and accelerate neural networks. Nevertheless, the high price and power consumption of these processors have resulted in drawing more attraction towards Field-Programmable Arrays (FPGAs). In order to improve resource...
High-Performance Architecture for Post-Quantum Cryptography Based on Elliptic Curve Isogeny
, Ph.D. Dissertation Sharif University of Technology ; Bayat Sarmadi, Siavash (Supervisor)
Abstract
Public-key cryptography is vital to secure digital communication. The classic instances of these cryptosystems are insecure against large-scale quantum computers. As a result, post-quantum cryptography has emerged as a replacement, which includes different categories. Isogeny-based schemes are one of the promising candidates mainly because of their smaller public key length. Due to high computational cost of such schemes, efficient implementations are significantly important. In this thesis, we have presented various solutions at three different abstraction layers. At the lowest layer, which deals with modular arithmetic, two hardware architectures are presented to perform modular...
Evaluating Effect of Number Representations on the Accuracy of Convolutional Neural Networks
, M.Sc. Thesis Sharif University of Technology ; Bayat Sarmadi, Siavash (Supervisor)
Abstract
Convolutional Neural Networks are a kind of neural network applicable in machine vision and image processing. The accuracy of these networks is dependent on different features such as network size network and input size. Today, researchers are improving the accuracy of neural networks by increasing their size. As a result, networks' computation will increase as well. The bigger the size of the neural network, the harder its hardware implementation. One of the proposed solutions to overcome this issue is to change the number representation while preserving the network accuracy. It's challenging to implement floating-point computation on hardware as it consumes a high amount of power and...
Fast Alignment-free Protein Comparison Approach based on FPGA Implementation
, M.Sc. Thesis Sharif University of Technology ; Koohi, Somayyeh (Supervisor)
Abstract
Protein, as the functional unit of the cell, plays a vital role in its biological function. With the advent of advanced sequencing techniques in recent years and the consequent exponential growth of the number of protein sequences extracted from diverse biological samples, their analysis, comparison, and classification have faced a considerable challenge. Existing methods for comparing proteins divide into two categories: methods based on alignment and alignment-free. Although alignment-based methods are among the most accurate methods, they face inherent limitations such as poor analysis of protein groups with low sequence similarity, time complexity, computational complexity, and memory...
Implementing a Software-Defined-Network Firewall on FPGA
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Software defined networks are developed to provide programmability and a centralized view in networks by decoupling control plane from data plane. Software defined networks are now well received,and these networks are evolving every day. This is while more attention has been paid to widen the application of these networks and eliminating the shortcomings in their performance. On the other hand, in very large networks, the issue of efficiency and processing speed is of great importance. However, performance in these networks is not satisfactory, especially in single controller based SDN due to the complex processing of packets in a unique controller. Security needs are also of great...
FPGA-Based Implementation of Deep Learning Accelerator with Concentration on Intrusion Detection Systems
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Intrusion Detection System (IDS) is an equipment destined to provide computer networks security. In recent years, Machine Learning and Deep Neural Network (DNN) methods have been considered as a way to detect new network attacks. Due to the huge amounts of calculations needed for these methods, there is a need for high performance and parallel or specific processors, such as Application Specific Integrated Circuit (ASIC), Graphical Processor Unit (GPU) and Field-Programmable Gate Array (FPGA). The latter seems more suitable than others due to its higher configurability and lesser power consumption. The goal of this study is the acceleration of a DNN-based IDS on FPGA. In this study, which is...
A Hardware-Software Partitioner for Deep Learning Algorithms
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
Deep learning, as a subdivision of machine learning, attempts to model high-level concepts by using a deep graph, consisting of several layers of linear and nonlinear transformations. Implementing these algorithms on hardware is a big challenge.¬This project offers a system in which various hardware methodologies can be used to implement deep learning algorithms side by side. The overall structure of the system consists of high-level programming interfaces for implementation and expression of machine learning algorithms by the user, which will be available as libraries in a high-level programming language such as Python, Ruby, and Julia. These interfaces allow the user to evaluate their...
Hardware Acceleration of Deep Learning based Firewalls Using FPGA
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
In recent years, due to the drawback of rule-based firewalls in detecting unknown attacks, using neural networks has got more attention to be used in firewalls. As the computation load of neural networks are so much there is a need to decrease the processing time and power consumption as they are under load 24/7. Although there have been huge achievements in the usage of graphics processing units (which contain numerous processing cores) in neural networks, their high power consumption has made the scientists think about an alternative to implement neural networks. Field Programmable Gate Array (FPGA) is one of the most serious candidates to be used for implementing neural networks. The goal...
A Power Efficient Routing Architecture for Reconfigurable Device
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
FPGA is a suitable substrate for implementation of embedded systems, mobiles, and hand-held devices due to cost reduction for \emph{Non-Recurring Engineering (NRE)}, short time to market, design flexibility, and reprogramming capability. Significant downscaling of CMOS technology feature size has led to static power growth rate, which is a limiting factor in further scaling. Previous studies aimed at reducing power consumption, mainly have focused on the power consumption of logical resources. However, proposing a low power architecture in routing network affects the power consumption of FPGAs significantly, because of the dominant power consumption in the routing network. This thesis...
An Efficient Reconfigurable Architecture to Speed up Machine Learning Algorithms
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
Machine learning algorithms are achieving state-of-the-art performance in many various applications such as image processing, machine vision, speech recognition, diagnosis diseases, robotics, military, and aerospace. For decades, the usage of machine learning algorithms especially Neural Network Algorithms (NNA) has been restricted due to their complexity and high computation time of available inefficient hardwares. Although advances in technology and the emergence of powerful processors has increased the usage of NNAs, especially Deep Neuaral Networks (DNNs), the research gap in machine learning hardware platform with high performance as well as high energy efficiency is still remaining....
Accelerating Big Data Stream Processing by FPGA-implementation of Parts of the Topology Graph
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
In recent years, big data processing plays an important role in the era of information technology. The exponential growth of big data volume increases the need for data centers and infrastructures with more processing power. Due to dark silicon and scalability limitations in deep-submicron, the increasing trend of server performance slows down. Therefore, hardware accelerators such as FPGA and GPU are become increasingly popular for improvement of data center processing power. There are two types of big data processing based on the application: stream processing and batch processing. With the widespread use of social networks, online control systems and internet of things services, the...
Using FPGA as Accelerator for Processing Units in Big Data Stream Processing Engine
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Distributed stream processing frameworks (DSPFs) are used for real-time processing of big data. Apache Storm is one of the most popular stream processing systems in industry today. By increasing data generation rate we need new methods to overcome processing requirements of DSPFs like Apache Storm. In this thesis we investigate the feasibility of incorporation FPGA acceleration into Apache Storm. Using FPGAs as co-processors in powerful servers can improve performance and accelerate processing of streaming data by increasing parallelism, decreasing processing time of each processing units and decreasing communication delay between these units. Our design includes a hardware part that...