Sharif Digital Repository

Public-key plays a significant role in today's communication over the network. However, current state-of-the-art public-key encryption (PKE) schemes are too complex to be efficiently employed in resource-constrained devices. Moreover, they are vulnerable to quantum attacks and soon will not have the required security. In the last decade, lattice-based cryptography has been a progenitor platform of the post-quantum cryptography (PQC) due to its lower complexity, which makes it more suitable for Internet of Things applications. In this article, we propose an efficient implementation of the binary learning with errors over ring (Ring-BinLWE) on the reduced instruction set computer-five (RISC-V)... 

Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times... 

Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to... 

Public key cryptography lies among the most important bases of security protocols. The classic instances of these cryptosystems are no longer secure when a large-scale quantum computer emerges. These cryptosystems must be replaced by post-quantum ones, such as isogeny-based cryptographic schemes. Supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE) are two of the most important such schemes. To improve the performance of these protocols, we have designed several modular multipliers. These multipliers have been implemented for all the prime fields used in SIKE round 3, on a Virtex-7 FPGA, showing a time and area-time product improvement of up to 60.1% and 64.5%,... 

We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times... 

The method for modeling switching converters plays a key role in real-time simulators. Associate discrete circuit (ADC) modeling technique is a commonly used method for modeling the switching converter. However, the optimal selection of the ADC-based switch model parameters has great importance in the accuracy of the real-time simulator. In this paper, the design of a real-time simulator for a switching power converter has been done, in which a novel method for detecting optimum values of the switch model parameters has been expressed. Particle swarm optimization (PSO) algorithm is used to find these optimum values using state-space analysis of the modeled circuit in the z-domain. The... 

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA... 

Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

Isogeny-based cryptography is one of the promising post-quantum candidates mainly because of its smaller public key length. Due to its high computational cost, efficient implementations are significantly important. In this paper, we have proposed a high-speed FPGA implementation of the supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE). To this end, we have adapted the algorithm of finding optimal large-degree isogeny computation strategy for hardware implementations. Using this algorithm, hardware-suited strategies (HSSs) can be devised. We have also developed a tool to schedule field arithmetic operations efficiently using constraint programming. This tool enables... 

This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some IPs are provided by trusted and some by untrusted sources. It suffices that a ring-oscillator based sensor is conveniently routed next to a signal that carries secret information (for instance, a cryptographic key), for this information to possibly get leaked. To address this security concern, we apply several different strategies and evaluate them on benchmark circuits from Verilog-to-Routing tool suite. Our experiments show that, for a... 

The elliptic curve cryptography (ECC) has gained attention mainly due to its lower complexity compared to other asymmetric methods while providing the same security level. The most performance critical operation in ECC is the point multiplication. Thus, its efficient implementation is desirable. One of the most secure and lightweight ECC curves, which satisfies all standard security criteria, is the Curve25519. In this paper, a low latency Karatsuba-Ofman-based field multiplier (KOM) and an efficient point multiplication over Curve25519 have been proposed. The improvements have been achieved mainly due to the proposed low latency pipelined KOM and efficient scheduling of field operations.... 

Field-Programmable Gate Arrays (FPGAs) employ a significant amount of SRAM cells in order to provide a flexible routing architecture. While this flexibility allows for a rather easy realization of arbitrary functionality, the respectively required cells significantly increase the area and power consumption of the FPGA. At the same time, it can be observed that full routing flexibility is frequently not needed in order to efficiently realize the desired functionality. In this work, we are proposing an FPGA realization which focuses on what is needed and realizes only a subset of the possible routing options using what we call Turn-Restricted Switch-Boxes. While this may yield a slight... 

A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequency-phase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-of-phase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of... 

By exponential increase in applications of the Internet of Things (IoT), such as smart ecosystems or e-health, more security threats have been introduced. In order to resist known attacks for IoT networks, multiple security protocols must be established among nodes. Thus, IoT devices are required to execute various cryptographic operations, such as public key encryption/decryption. However, classic public key cryptosystems, such as Rivest-Shammir-Adlemon and elliptic curve cryptography are computationally more complex to be efficiently implemented on IoT devices and are vulnerable regarding quantum attacks. Therefore, after complete development of quantum computing, these cryptosystems will... 

Large-scale simulation of spiking neural networks on hardware with a remarkable resemblance to their mathematical models is a key objective of the neuromorphic discipline. This issue is, however, considerably resource-intensive due to the presence of nonlinear terms in neuron models. This paper proposes a novel uniform piecewise linear segmentation approach for nonlinear function evaluations. Employing the proposed approach, we present a uniform-segmented adaptive exponential neuron model capable of accurately producing various responses exhibited by the original model and suitable for efficient large-scale implementation. In contrast to previous nonuniform-segmented neuron models, the... 

Orthogonal Matching Pursuit is an iterative greedy algorithm used to find a sparse approximation for high-dimensional signals. The algorithm is most popularly used in Compressive Sensing, which allows for the reconstruction of sparse signals at rates lower than the Shannon-Nyquist frequency, which has traditionally been used in a number of applications such as MRI and computer vision and is increasingly finding its way into Big Data and data center analytics. OMP traditionally suffers from being computationally intensive and time-consuming, this is particularly a problem in the area of Big Data where the demand for computational resources continues to grow. In this paper, the data-level... 

In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low design cost and short time-to-market. Besides their vulnerability to hardware Trojan attacks, SRAM-based reconfigurable devices are also significantly susceptible to faults originated by particle strikes. There have been various methods to mitigate either hardware Trojan attacks or faults. To our knowledge, however, no method has been presented that can integrate detecting, distinguishing, and mitigating faults and Trojans. In this paper, we... 

During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5,... 

Efficient hardware realization of spiking neural networks is of great significance in a wide variety of applications, such as high-speed modeling and simulation of large-scale neural systems. Exploiting the key features of FPGAS, this paper presents a novel nonlinear function evaluation approach, based on an effective uniform piecewise linear segmentation method, to efficiently approximate the nonlinear terms of neuron and synaptic plasticity models targeting low-cost digital implementation. The proposed approach takes advantage of a high-speed and extremely simple segment address encoder unit regardless of the number of segments, and therefore is capable of accurately approximating a given...