Search for: hardware-architecture
0.007 seconds

    VLSI Architecture for Base Band Part of an Optical OFDM Transceiver

    , M.Sc. Thesis Sharif University of Technology Ghanaatian Jahromi, Reza (Author) ; Shabany, Mahdi (Supervisor) ; Salehi, Javad (Supervisor)
    Optical Communication is a promising technology in access networks because of bandwidth hungry application like videos. So fiber Optic is an important candidate as a media in networks. There are different methods of modulation for transferring data through a channel. Among all, Orthogonal Frequency Division Multiplexing is a method which used in most wired and wireless systems. Recent researches show that OFDM is also a good approach for optical communication.
    In this thesis we concentrate on hardware implementation of digital part of an Optical OFDM transceiver. In the first step we ignore the effect of optical channel and design and simulate the transmitter and receiver. After that we... 

    Efficient implementation of real-time ECG derived respiration system using cubic spline interpolation

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 1083-1086 ; 02714310 (ISSN) ; 9781467357609 (ISBN) Shayei, A ; Ehsani, S. P ; Shabany, M ; Sharif University of Technology
    Monitoring the respiratory signal is crucial in many medical applications. Traditional methods for the respiration measurement are normally based on measuring the volume of air inhaled and exhaled by lungs (like spirometer) or oxygen saturation in blood. However, these methods have numerous challenges including their high cost and not being accessible in some cases. In this paper, an algorithm for deriving the respiratory signal from ECG signal is proposed, which is based on other proposed algotithms. This algorithm uses the cubic spline interpolation (CSI) of R-waves in ECG to derive the respiratory signal. The CSI algorithm is made efficient with respect to ECG features in order to reduce... 

    A high performance real-time simulator for controllers hardware-in-the-loop testing

    , Article Energies ; Volume 5, Issue 6 , 2012 , Pages 1713-1733 ; 19961073 (ISSN) Matar, M ; Karimi, H ; Etemadi, A ; Iravani, R ; Sharif University of Technology
    This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The... 

    LDMBL: An architecture for reducing code duplication in heavyweight binary instrumentations

    , Article Software - Practice and Experience ; Volume 48, Issue 9 , 2018 , Pages 1642-1659 ; 00380644 (ISSN) Momeni, B ; Kharrazi, M ; Sharif University of Technology
    John Wiley and Sons Ltd  2018
    Emergence of instrumentation frameworks has vastly contributed to the software engineering practices. As the instrumentation use cases become more complex, complexity of instrumenting programs also increases, leading to a higher risk of software defects, increased development time, and decreased maintainability. In security applications such as symbolic execution and taint analysis, which need to instrument a large number of instruction types, this complexity is prominent. This paper presents an architecture based on the Pin binary instrumentation framework to abstract the low-level OS and hardware-dependent implementation details, facilitate code reuse in heavyweight instrumentation use... 

    Reliable hardware architectures for efficient secure hash functions ECHO and fugue

    , Article 15th ACM International Conference on Computing Frontiers, CF 2018, 8 May 2018 through 10 May 2018 ; 2018 , Pages 204-207 ; 9781450357616 (ISBN) Mozaffari Kermani, M ; Azarderakhsh, R ; Bayat Sarmadi, S ; ACM Special Interest Group on Microarchitectural Research and Processing (SIGMICRO) ; Sharif University of Technology
    Association for Computing Machinery, Inc  2018
    In cryptographic engineering, extensive attention has been devoted to ameliorating the performance and security of the algorithms within. Nonetheless, in the state-of-the-art, the approaches for increasing the reliability of the efficient hash functions ECHO and Fugue have not been presented to date.We propose efficient fault detection schemes by presenting closed formulations for the predicted signatures of different transformations in these algorithms. These signatures are derived to achieve low overhead for the specific transformations and can be tailored to include byte/word-wide predicted signatures. Through simulations, we show that the proposed fault detection schemes are... 

    Parallel hermite interpolation on the pyramid

    , Article 22nd International Symposium on Computer and Information Sciences, ISCIS 2007, Ankara, 7 November 2007 through 9 November 2007 ; February , 2007 , Pages 403-407 ; 1424413648 (ISBN); 9781424413645 (ISBN) Larijani, E ; Sarbazi Azad, H ; Sharif University of Technology
    The pyramid network is one of the most important interconnection topologies used as hardware architecture or software data structure. It has a combined tree-mesh structure making it suitable for solving many parallel problems and applications. This paper proposes a parallel algorithm for Hermite Interpolation on the Pyramid network which has at least N nodes. The proposed algorithm has 3 phases: initialization, main, and final. The algorithm is optimal with a time complexity of O(N) for an N-point interpolation. ©2007 IEEE  

    Performance evaluation of communication networks for parallel and distributed systems

    , Article Parallel Computing ; Volume 32, Issue 11-12 , 2006 , Pages 775-776 ; 01678191 (ISSN) Sarbazi Azad, H ; Ould Khaoua, M ; Zomaya, A. Y ; Sharif University of Technology

    Hardware architecture for supersingular isogeny diffie-hellman and key encapsulation using a fast montgomery multiplier

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 68, Issue 5 , 2021 , Pages 2042-2050 ; 15498328 (ISSN) Farzam, M. H ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Alivand, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Public key cryptography lies among the most important bases of security protocols. The classic instances of these cryptosystems are no longer secure when a large-scale quantum computer emerges. These cryptosystems must be replaced by post-quantum ones, such as isogeny-based cryptographic schemes. Supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE) are two of the most important such schemes. To improve the performance of these protocols, we have designed several modular multipliers. These multipliers have been implemented for all the prime fields used in SIKE round 3, on a Virtex-7 FPGA, showing a time and area-time product improvement of up to 60.1% and 64.5%,...