Search for: hardware-security
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    Secure Implementation of Cryptographic Algorithms on FPGA

    , M.Sc. Thesis Sharif University of Technology Farzam, Mohammad-Hossein (Author) ; Bayat-Sarmadi, Siavash (Supervisor)
    Security of cryptographic devices lies amongst the most important issues in the field of hardware security. It is frequently seen that in the process of designing cryptographic systems insufficient attention is paid to the physical implementation details. This is happening while a lot of secret information is known to be leaked through side-channels such as power consumption, electromagnetic emission and execution time. Side-channel attacks are able to reveal secret keys by using these side-channel leakages. Additionally, side-channel attacks are one of the most powerful but low-cost attacks that put the security of cryptographic systems in vain. It can be claimed that the most dangerous... 

    An Efficient Hardware Trojan Detector Using On-chip Ring Oscillator

    , M.Sc. Thesis Sharif University of Technology Khodadadi, Mohsen (Author) ; Hesabi, Shahin (Supervisor)
    Nowadays integrated circuits are extremely vulnerable to hardware trojans (HT). Hardware trojans can be injected into the ICs in design or fabricate phase, and damage system’s functionality or security. In this thesis, we first describe hardware trojan definition, classification and types of HTs, negative effects, detection ways and analysis of them. Then we propose a new solution in order to solve the negative points of previous methods  

    Design of Reconfigurable Hardware Security Module Based on Network Protocol Detection

    , M.Sc. Thesis Sharif University of Technology Zohouri, Hamid Reza (Author) ; Jahangir, Amir Hossein (Supervisor)
    Nowadays, in the presence of different types of computer attacks and different methods of eavesdropping on network communications, nobody can deny the importance of cryptography. Hardware Security Modules that are specifically designed for this purpose are widely used as a fast and reliable tool for encrypting data in computer networks. In this project, using the common and well-known FPGA platform and by leveraging the reconfigurability feature of this platform and also by adding a network protocol detection module to the traditional architecture of Hardware Security Modules, a novel module has been designed and implemented that can encrypt and decrypt data in a communication network, at... 

    A Scan Chain-Based Aging Monitoring Scheme for Detection of Recycled Chips

    , M.Sc. Thesis Sharif University of Technology Ostovar, Atanaz (Author) ; Hesabi, Shahin (Supervisor)
    Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different... 

    Hardware Trojan detection and localization based on local detectors

    , Article Turkish Journal of Electrical Engineering and Computer Sciences ; Volume 26, Issue 3 , 2018 , Pages 1403-1416 ; 13000632 (ISSN) Bazzazi, A ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
    Turkiye Klinikleri Journal of Medical Sciences  2018
    Hardware Trojans are one of the serious threats with detrimental, irreparable effects on the functionality, security, and performance of digital integrated circuits. It is difficult to detect Trojans because of their diversity in size and performance. While the majority of current methods focus on Trojan detection during chip testing, run-time techniques can be employed to gain unique advantages. This paper proposes a method based on the online scalable detection technique, which eliminates the need for a reference chip. Involving local detectors, this technique assesses the variations in the logical values of each node to find out whether there are Trojans. This method excludes time and... 

    Hardware trojan detection based on logical testing

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 33, Issue 4 , 2017 , Pages 381-395 ; 09238174 (ISSN) Bazzazi, A ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
    Springer New York LLC  2017
    In recent years, hardware Trojans (HTs) have become one of the main challenging concerns within the chain of manufacturing digital integrated circuit chips. Because of their diversity in chips, HTs are difficult to detect and locate. This paper attempted to propose a new improved method for detection and localization of HTs based on the real-time logical values of nodes. The algorithm extracts the nodes with special attributes. At the next stage, the nodes with the greatest similarity in terms of logical value are selected as targets. Depending on the size of the circuit, the extraction continues until a sufficient number of similar nodes has been selected. The logical relationship between... 

    A unified approach to detect and distinguish hardware trojans and faults in sram-based fpgas

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 35, Issue 2 , 2019 , Pages 201-214 ; 09238174 (ISSN) Ranjbar, O ; Bayat Sarmadi, S ; Pooyan, F ; Asadi, H ; Sharif University of Technology
    Springer New York LLC  2019
    In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low design cost and short time-to-market. Besides their vulnerability to hardware Trojan attacks, SRAM-based reconfigurable devices are also significantly susceptible to faults originated by particle strikes. There have been various methods to mitigate either hardware Trojan attacks or faults. To our knowledge, however, no method has been presented that can integrate detecting, distinguishing, and mitigating faults and Trojans. In this paper, we... 

    PUF-based solutions for secure communications in advanced metering infrastructure (AMI)

    , Article International Journal of Communication Systems ; Volume 30, Issue 9 , 2017 ; 10745351 (ISSN) Delavar, M ; Mirzakuchaki, S ; Ameri, M. H ; Mohajeri, J ; Sharif University of Technology
    John Wiley and Sons Ltd  2017
    Advanced metering infrastructure (AMI) provides 2-way communications between the utility and the smart meters. Developing authenticated key exchange (AKE) and broadcast authentication (BA) protocols is essential to provide secure communications in AMI. The security of all existing cryptographic protocols is based on the assumption that secret information is stored in the nonvolatile memories. In the AMI, the attackers can obtain some or all of the stored secret information from memories by a great variety of inexpensive and fast side-channel attacks. Thus, all existing AKE and BA protocols are no longer secure. In this paper, we investigate how to develop secure AKE and BA protocols in the... 

    Provably secure and efficient PUF-based broadcast authentication schemes for smart grid applications

    , Article International Journal of Communication Systems ; Volume 32, Issue 8 , 2019 ; 10745351 (ISSN) Ameri, M. H ; Delavar, M ; Mohajeri, J ; Sharif University of Technology
    John Wiley and Sons Ltd  2019
    Many smart grid applications need broadcast communications. Because of the critical role of the broadcasted messages in these applications, their authentication is very important to prevent message forgery attacks. Smart grid consists of plenty of low-resource devices such as smart meters or phasor measurement units (PMUs) that are located in physically unprotected environments. Therefore, the storage and computational constraints of these devices as well as their security against physical attacks must be considered in designing broadcast authentication schemes. In this paper, we consider two communication models based on the resources of the broadcasters and receivers and propose a physical... 

    HDL based simulation framework for a DPA secured embedded system

    , Article CSI Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2015, 7 October 2015 through 8 October 2015 ; October , 2015 , Page(s): 1 - 6 ; 9781467380478 (ISBN) Kamran, D ; Marjovi, A ; Fanian, A ; Safayani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Side Channel Analysis (SCA) are still harmful threats against security of embedded systems. Due to the fact that every kind of SCA attack or countermeasure against it needs to be implemented before evaluation, a huge amount of time and cost of this process is paid for providing high resolution measurement tools, calibrating them and also implementation of proposed design on ASIC or target platform. In this paper, we have introduced a novel simulation platform for evaluation of power based SCA attacks and countermeasures. We have used Synopsys power analysis tools in order to simulate a processor and implement a successful Differential Power Analysis (DPA) attack on it. Then we focused on the... 

    FPGA-based protection scheme against hardware trojan horse insertion using dummy logic

    , Article IEEE Embedded Systems Letters ; Volume 7, Issue 2 , 2015 , Pages 46-50 ; 19430663 (ISSN) Khaleghi, B ; Ahari, A ; Asadi, H ; Bayat-Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed scheme, we identify the unused resources at the device layout-level and offer dummy logic cells for different resources. The proposed HTH protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that by employing the proposed HTH... 

    A bio-inspired method for hardware Trojan detection

    , Article 2017 19th International Symposium on Computer Architecture and Digital Systems, CADS 2017 ; Volume 2018-January , 8 March , 2018 , Pages 1-2 ; 9781538643792 (ISBN) Farajipour Ghohroud, N ; Hessabi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Outsourcing the ICs for manufacturing introduces potential security threats such as hardware Trojans (HTs). In this paper, we propose hardware-based artificial immune system for solving this problem. This system uses a biologically-inspired technique which makes it attractive for using in computer security systems. Using our proposed method, the probability of HT detection can reach 100 percent, and the system can be made immune against HTs. © 2017 IEEE  

    Post-quantum cryptoprocessors optimized for edge and resource-constrained devices in IoT

    , Article IEEE Internet of Things Journal ; Volume 6, Issue 3 , 2019 , Pages 5500-5507 ; 23274662 (ISSN) Ebrahimi, S ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    By exponential increase in applications of the Internet of Things (IoT), such as smart ecosystems or e-health, more security threats have been introduced. In order to resist known attacks for IoT networks, multiple security protocols must be established among nodes. Thus, IoT devices are required to execute various cryptographic operations, such as public key encryption/decryption. However, classic public key cryptosystems, such as Rivest-Shammir-Adlemon and elliptic curve cryptography are computationally more complex to be efficiently implemented on IoT devices and are vulnerable regarding quantum attacks. Therefore, after complete development of quantum computing, these cryptosystems will... 

    Lightweight and DPA-resistant post-quantum cryptoprocessor based on binary ring-LWE

    , Article 20th International Symposium on Computer Architecture and Digital Systems, CADS 2020, 19 August 2020 through 20 August 2020 ; 2020 Ebrahimi, S ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    With the exponential growth in the internet of things (IoT) applications such as smart city and e-health, more embedded devices and smart nodes are connected to the network. In order to provide security for such resource-constrained devices, different cryptographic schemes such as public key encryption (PKE) are required. However, considering the high complexity and vulnerability of classic PKE schemes against quantum attacks, it is necessary to consider other possible options. Recently, lattice-based cryptography and especially learning with errors (LWE) have gained high attention due to resistance against quantum attacks and relatively low-complexity operations. During the past decade,... 

    Trojan counteraction in hardware: A survey and new taxonomy

    , Article Indian Journal of Science and Technology ; Volume 9, Issue 18 , 2016 ; 09746846 (ISSN) Bazzazi, A ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
    Indian Society for Education and Environment  2016
    The widespread expansion of the semiconductor industry and various production phases have led to the increased importance of fabricating highly secure chips. Both in factories manufacturing and later at actual operation, digital integrated circuits (IC) might encounter a variety of hardware attacks, one type of which involves Hardware Trojans (HT). Due to their diversity, it has become a major hardware security challenge to prevent, detect and track down HTs. In this regard, the first step is to understand the taxonomy of Trojans and the current ways in which they can be encountered. For that purpose, certain classifications are required. With their downsized dimensions, the Trojans have... 

    A ring oscillator-based PUF with enhanced challenge-response pairs

    , Article Canadian Journal of Electrical and Computer Engineering ; Volume 39, Issue 2 , 2016 , Pages 174-180 ; 08408688 (ISSN) Delavar, M ; Mirzakuchaki, S ; Mohajeri, J ; Sharif University of Technology
    IEEE Canada  2016
    Physical unclonable functions (PUFs) are powerful security primitives that provide cheap and secure solutions for security-related applications. Strong PUFs provide a large set of challenge-response pairs (CRPs) and are suitable for device authentication. Weak PUFs produce a small number of CRPs and can be used for key extraction. In this paper, we propose a novel method to enhance the CRP set of traditional ring oscillator-based PUFs (RO-PUFs). RO-PUFs are one of the most reliable types of PUFs and the best fit to implement on the field-programmable gate arrays. To the best of our knowledge, our method provides the maximum number of CRPs compared with the state of the art. In addition, the... 

    Improving hardware Trojan detection using scan chain based ring oscillators

    , Article Microprocessors and Microsystems ; Volume 63 , 2018 , Pages 55-65 ; 01419331 (ISSN) Asadi Kouhanjani, M. R ; Jahangir, A. H ; Sharif University of Technology
    Elsevier B.V  2018
    In recent years, the security of integrated circuits (ICs) has received more attention as usage of ICs made by untrustworthy foundries has increased in safety-critical systems [1]. In this paper, we introduce a novel approach for fingerprinting the delay of functional paths in a sequential circuit that have millions of transistors, like processors. We present a method for inserting Ring Oscillators (ROs) into scan chain for measuring the delay of each functional path inside the chip. Using the proposed method, the payload part of Trojans will be detected according to their size and cell types. Our method can be used by power-based Trojan detection approaches for finding the trigger part of... 

    Behavioral-level hardware trust: analysis and enhancement

    , Article Microprocessors and Microsystems ; Volume 58 , 2018 , Pages 24-33 ; 01419331 (ISSN) Farajipour Ghohroud, N ; Hessabi, S ; Sharif University of Technology
    Elsevier B.V  2018
    Hardware IPs are mostly presented in Register Transfer Level (RTL) description. Although considerable attention has been paid to hardware Trojan detection and design-for-trust at gate level and lower levels, so far there have been few methods at RT Level and behavioral RTL. We propose an approach to analyze circuit susceptibility to Trojan at the behavioral level, based on controllability analysis. We propose three design-for-trust methods, which reduce circuit vulnerability to hardware Trojans by increasing the probability of Trojan detection. We use side-channel Trojan detection method based on power consumption to evaluate Trojan detection probability. Our proposed methods can improve... 

    Reliable hardware architectures for efficient secure hash functions ECHO and fugue

    , Article 15th ACM International Conference on Computing Frontiers, CF 2018, 8 May 2018 through 10 May 2018 ; 2018 , Pages 204-207 ; 9781450357616 (ISBN) Mozaffari Kermani, M ; Azarderakhsh, R ; Bayat Sarmadi, S ; ACM Special Interest Group on Microarchitectural Research and Processing (SIGMICRO) ; Sharif University of Technology
    Association for Computing Machinery, Inc  2018
    In cryptographic engineering, extensive attention has been devoted to ameliorating the performance and security of the algorithms within. Nonetheless, in the state-of-the-art, the approaches for increasing the reliability of the efficient hash functions ECHO and Fugue have not been presented to date.We propose efficient fault detection schemes by presenting closed formulations for the predicted signatures of different transformations in these algorithms. These signatures are derived to achieve low overhead for the specific transformations and can be tailored to include byte/word-wide predicted signatures. Through simulations, we show that the proposed fault detection schemes are... 

    On constrained implementation of lattice-based cryptographic primitives and schemes on smart cards

    , Article ACM Transactions on Embedded Computing Systems ; Volume 14, Issue 3 , 2015 ; 15399087 (ISSN) Boorghany, A ; Sarmadi, S. B ; Jalili, R ; Sharif University of Technology
    Association for Computing Machinery  2015
    Most lattice-based cryptographic schemes with a security proof suffer from large key sizes and heavy computations. This is also true for the simpler case of authentication protocols that are used on smart cards as a very-constrained computing environment. Recent progress on ideal lattices has significantly improved the efficiency and made it possible to implement practical lattice-based cryptography on constrained devices. However, to the best of our knowledge, no previous attempts have been made to implement lattice-based schemes on smart cards. In this article, we provide the results of our implementation of several state-of-the art lattice-based authentication protocols on smart cards and...