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Work-in-progress: heterogeneous redundancy to address performance and cost in multi-core SIMT
, Article 2017 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2017, 15 October 2017 through 20 October 2017 ; 2017 ; 9781450351850 (ISBN) ; Mozafari, S. H ; Hessabi, S ; Sharif University of Technology
Abstract
As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. © 2017 ACM
Work-in-Progress: heterogeneous redundancy to address performance and cost in multi-core SIMT
, Article Proceedings of the 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES 2017, 15 October 2017 through 20 October 2017 ; 2017 ; 9781450351850 (ISBN) ; Mozafari, S. H ; Hessabi, S ; Sharif University of Technology
Abstract
As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM)