Sharif Digital Repository

In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low design cost and short time-to-market. Besides their vulnerability to hardware Trojan attacks, SRAM-based reconfigurable devices are also significantly susceptible to faults originated by particle strikes. There have been various methods to mitigate either hardware Trojan attacks or faults. To our knowledge, however, no method has been presented that can integrate detecting, distinguishing, and mitigating faults and Trojans. In this paper, we... 

The objective of the present study is to investigate the capability of field-programmable gate array hardware in numerical simulation of a model of a dielectric barrier discharge plasma actuator to accelerate the calculations. The reconfigurable hardware is designed such that it is possible to reprogram its architecture after manufacturing. This provides the capability to design and implement various architectures for several applications. Two reconfigurable chips are used in the present study, one of which consists of a programmable logic unit and a typical microprocessor. This hybrid architecture makes the high performance of the reconfigurable hardware in custom computing and the... 

Application of piezoelectric materials in vibration energy harvesters is expanding rapidly, especially in MEMS-based devices, due to their uncomplicated fabrication processes and reasonable power generation potential. In addition to standard power extraction methods, nonlinear switched techniques with capability of generated power enhancement, are previously developed and extensively applied in energy harvesting using piezoelectric materials. In this article, vibratory behavior of bimorph resonant harvesters coupled to nonlinear circuits of energy harvesting including standard and switched techniques is investigated. An analytical approach employing some perturbation technique, is utilized... 

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of... 

In distribution systems, feeder reconfiguration (FR) can lead to loss reduction, reliability improvement and some other economic savings. These advantages can be intensified by proper control and switching of Capacitor Banks (CBs). In this paper, using Ant Colony Optimization (ACO) technique, a novel method is proposed for simultaneous dynamic scheduling of FR and CB switching in the presence of DG units having uncertain and variant generations over time. This method is applicable to both smart and classic distribution systems. While for the latter, state estimation method should be used to estimate the loads at different buses by employing a limited number of measurements. The objective of... 

The main purpose of this paper is to investigate the feasibility of using field programmable gate arrays (FPGAs) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the fluid dynamics differential equations. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is a system on a chip FPGA type that integrates both microprocessor and FPGA architectures into a single device. In this paper, typical computational fluid dynamics... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

An ultra-broadband absorber of light is proposed by using periodic array of ultra-thin metallic ribbons on top of a lossless quarter-wavelength dielectric spacer placed on a metallic reflector. We propose a fully analytical circuit model for the structure, and then the absorber is duly designed based on the impedance matching concept. As a result, normalized bandwidth of 99.5% is realized by the proposed absorbing structure in mid-infrared regime. Performing a numerical optimization algorithm, we could also reach to normalized bandwidth of 103%  

This paper describes the concept and a sample design of a broadband loaded monopole antenna with a novel matching network integrated with the antenna body. The proposed monopole antenna is designed by loading three different lumped loads integrated on a wire antenna and a simple input matching network. Parameters of the matching circuits and the lumped loads optimized by using a genetic algorithm (GA). The proposed antenna loads and the matching network is integrated into the antenna body by the use of printed circuit technology making the antenna fabrication process easy. A prototype of the proposed 1.19-meter monopole antenna is fabricated and measured. The simulation and measurement... 

Recently, an increasing concern has been raised about turn-to-turn faults (TTFs) in power transformers, because these faults can lead to severe transformer insulation failure and consequently, its outage. Generally, it is impossible to experimentally analyze the transformer behavior under such faults, since the implementation of those experiments may be substantially destructive. Therefore, computer-aided models should be developed to investigate the performance of transformer protective relays under turn-to-turn faults. So far, existing transformer models are mainly formulated to implement in the EMTP-based softwares. However, most of power system protection engineers and researchers... 

This study proposes a new fault detection method for modular multilevel converter (MMC) semiconductor power switches. While in common MMCs, the cells capacitor voltages are measured directly for control purposes, in this study voltage measurement point changes to the cell output terminal improving fault diagnosis ability. Based on this measurement reconfiguration, a novel fault detection algorithm is designed for MMCs semiconductor power switches. The open circuit and short circuit faults are detected based on unconformity between modules output voltage and switching signals. Simulation and experimental results confirm accurate and fast operation of the proposed method in faulty cell... 

In this paper, a novel method for high-repetition-rate high-power radio frequency (RF) pulse generation, which involves only passive solid-state devices and is capable of being used for generating high power microwaves using a low-to-high power converting scheme based on nonlinear self-compression is proposed. The method is also expected to be of low jitter. In the proposed circuit, two high voltage diodes with proper reverse recovery characteristics are used. The simulation results show that the proposed circuit generates RF pulses, with central frequencies up to gigahertz range. By applying a sub-kilowatt power supply, the maximum output power was well over 10 kW. This power can be... 

It has been attempted to gain a new viewpoint in transient cell modeling of vanadium redox flow battery. This has been achieved by considering electrochemical relations along with conceptual electrical circuit of this kind of battery. The redox flow battery is one of the best rechargeable batteries because of its capability to average loads and output power sources. A model of transient behavior is presented in this paper. The transient features are considered as the most remarkable characteristics of the battery. The chemical reactions, fluid flow, and electrical circuit of the structure govern the dynamics. The transient behavior of the redox flow battery based on chemical reactions is... 

Design techniques to enhance bandwidth and linearity of broadband multistage low-noise amplifiers (LNAs) are presented. A feedback amplifier circuit is proposed to compensate for transistor gain roll-off with frequency in other amplifier stages and extend overall bandwidth. Moreover, a transistor width tapering in a multistage LNA is applied to improve linearity. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA implemented in a 0.1-μm GaAs pHEMT process. The LNA features 18-43 GHz bandwidth, 21.6 dB average gain, and 1.8-2.7 noise figure (NF). It exhibits output 1-dB compression point of 11.5 dBm at 30 GHz and consumes 70 mA bias current from a... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we... 

Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration... 

Recent developments in improving lighting efficiency and cost reduction of LEDs have made them suitable alternatives to the current lighting systems. In this paper, a novel offline structure is proposed to drive LEDs. The proposed circuit has a high-input power factor, high efficiency, a long lifetime, and it produces no flicker. To increase the lifetime of the converter, the proposed circuit does not include any electrolytic capacitors in the power stage. The proposed circuit consists of a transition mode flyback converter in order to improve power factor. Additionally, a buck converter is added to the third winding of the flyback transformer in order to create two parallel paths for the... 

Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement... 

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with...