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reconfigurable-hardware
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Accelerating Numerical Solution of Steady and Unsteady Equations Using FPGA
, Ph.D. Dissertation Sharif University of Technology ; Ebrahimi, Abbas (Supervisor)
Abstract
Nowadays one of the main challenges facing fluid dynamics simulations is the long duration of numerical calculations. The goal of this research is to use FPGAs (Field Programmable Gate Arrays) to accelerate fluid dynamics solutions. First, the ability of FPGAs in mathematical operations on floating point numbers is studied. Then, various fluid dynamics problems are implemented on the FPGA hardware, and each one is solved separately. Unsteady 1D Couette problem, 2D potential flow (Laplace equation), incompressible viscous fluid flow over a backward facing step, and compressible inviscid flow over a bump are some of the problems in question. FPGA is an integrated circuit containing a number of...
Design of Reconfigurable Hardware Security Module Based on Network Protocol Detection
,
M.Sc. Thesis
Sharif University of Technology
;
Jahangir, Amir Hossein
(Supervisor)
Abstract
Nowadays, in the presence of different types of computer attacks and different methods of eavesdropping on network communications, nobody can deny the importance of cryptography. Hardware Security Modules that are specifically designed for this purpose are widely used as a fast and reliable tool for encrypting data in computer networks. In this project, using the common and well-known FPGA platform and by leveraging the reconfigurability feature of this platform and also by adding a network protocol detection module to the traditional architecture of Hardware Security Modules, a novel module has been designed and implemented that can encrypt and decrypt data in a communication network, at...
Reducing the Energy Consumption of the Embedded Real-Time Systems with Reconfigurable Components
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
Over the Recent Decade, the embedded systems have expanded to include a wide variety of products, ranging from digital cameras, to medical systems, to Radar and telecommunication systems, to sensor networks. Engineers strive to create ever smaller and faster products, many of which, such as battery operated systems, have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Dynamic reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems....
Towards dark silicon era in FPGAs using complementary hard logic design
, Article Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 ; Sept , 2014 , pp. 1 - 6 ; ISBN: 9783000446450 ; Khaleghi, B ; Ebrahimi, Z ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
Abstract
While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional...
FPGA-based reconfigurable control for fault-tolerant back-to-back converter without redundancy
, Article IEEE Transactions on Industrial Electronics ; Volume 60, Issue 8 , May , 2013 , Pages 3360-3371 ; 02780046 (ISSN) ; Poure, P ; Saadate, S ; Zolghadri, M. R ; Sharif University of Technology
2013
Abstract
In this paper, an FPGA-based fault-tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault-tolerant converter operates like a conventional back-to-back six-leg converter, and after the fault, it becomes a five-leg converter. Design, implementation, and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital...
Fault-tolerant five-leg converter topology with FPGA-Based reconfigurable control
, Article IEEE Transactions on Industrial Electronics ; Volume 60, Issue 6 , 2013 , Pages 2284-2294 ; 02780046 (ISSN) ; Poure, P ; Saadate, S ; Zolghadri, M. R ; Sharif University of Technology
2013
Abstract
Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable...
A partial task replication algorithm for fault-tolerant FPGA-based soft-multiprocessors
, Article CSI Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2015, 7 October 2015 through 8 October 2015 ; October , 2015 , Page(s): 1 - 7 ; 9781467380478 (ISBN) ; Farbeh, H ; Miremadi, S. G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
FPGA-based multiprocessors, referred as softmultiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in the configuration bits. The main of this method is to analyze the scheduled task graph and select a subset of tasks to be replicated in multiple processors based on the utilization of the processors in different execution phases. To this end, 1) errors are detected by re-executing a subset of tasks...
Collision-free path planning of a novel reconfigurable mobile parallel mechanism
, Article International Conference on Robotics and Mechatronics, ICROM 2015, 7 October 2015 through 9 October 2015 ; 2015 , Pages 389-394 ; 9781467372343 (ISBN) ; Kazemi, H ; Masouleh, M. T ; Novin, R. S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
This paper initially deals with the design of a new customized reconfigurable mobile parallel mechanism. This mechanism is called "Taar Reconfigurable ParaMobile (TRPM)", consisting of three mobile robots as the main actuators. Then, the kinematics and path planning for this mechanism are represented. The newly proposed mechanism is expected to circumvent some shortcomings of inspection operation in unknown environments with unexpected changes in their workspace, e.g., in a water pipe with non-uniform section area. In this paper, "Artificial Potential Field (APF)" has been assumed to be the path planning algorithm and its resulting attractive and repulsive forces are only applied to the...
Decentralized control of reconfigurable robots using joint-torque sensing
, Article International Conference on Robotics and Mechatronics, ICROM 2015, 7 October 2015 through 9 October 2015 ; 2015 , Pages 581-585 ; 9781467372343 (ISBN) ; Sharif University of Technology
Abstract
In this paper, a decentralized controller for trajectory tracking of modular and reconfigurable robot manipulators is developed. The proposed control scheme uses joint-torque sensory feedback; also sliding mode control is employed to make both position and velocity tracking errors of robot manipulators globally converging to zero. Proposed scheme also guarantees that all signals in closed-loop systems will be bounded. In contrast to some of prior works in this scheme, each controller uses a smooth law to achieve its purposes. In this method, each controller uses only local information for producing control law hence separated controller can be used to control each module of manipulator and...
DsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations
, Article International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, 4 October 2015 through 9 October 2015 ; Oct , 2015 , Pages 75-82 ; 9781467383219 (ISBN) ; Shafique, M ; Kriebel, F ; Rehman, S ; Tavana, M. K ; Ejlali, A ; Henkel, J ; ACM; IEEE ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM...
Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology
, Article Microprocessors and Microsystems ; April , 2016 ; 01419331 (ISSN) ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
Elsevier
2016
Abstract
Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the...
Traffic-aware buffer reconfiguration in on-chip networks
, Article IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 5 October 2015 through 7 October 2015 ; Volume 2015-October , 2015 , Pages 201-206 ; 23248432 (ISSN) ; 9781467391405 (ISBN) ; Sarbazi-Azad, H ; Sharif University of Technology
IEEE Computer Society
2015
Abstract
Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,...
Designing the FPGA-based system for Triangle Phase space Mapping (TPSM) of heart rate variability (HRV) signal
, Article 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015, 9 July 2015 through 11 July 2015 ; July , 2015 , Page(s): 1 - 4 ; 9781479984985 (ISBN) ; Moharreri, S ; Ghorshi, A ; Molnar K ; Herencsar N ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
There has been an increasing interest in telemonitoring thanks to the availability of new technologies for data transmission and processing with better performances and lower costs. In this paper, we try to develop and implement the HRV signal processing into a Field Programmable Gate Array (FPGA). The hardware implementing algorithm was developed in Verilog Hardware Description Language (HDL). In designed hardware, after defining the number of samples in the input, we extract and analyses the Triangular Phase Space Mapping (TPSM), a novel method for representation of heart rate. The performance of the system was tested using MATLAB and validated based on the input signals
An efficient reconfigurable architecture by characterizing most frequent logic functions
, Article 25th International Conference on Field Programmable Logic and Applications, FPL 2015, 2 September 2015 through 4 September 2015 ; Sept , 2015 , Page(s): 1 - 6 ; 9780993428005 (ISBN) ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity...
An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators
, Article Proceedings of the International Symposium on Low Power Electronics and Design, 22 July 2015 through 24 July 2015 ; Volume 2015-September , July , 2015 , Pages 249-254 ; 15334678 (ISSN) ; 9781467380096 (ISBN) ; Mirhosseini, A ; Aghilinasab, H ; Sarbazi Azad, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to...
DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations
, Article 20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, 22 July 2015 through 24 July 2015 ; Volume 2015 , September , 2015 , Pages 225-230 ; 15334678 (ISSN) ; 9781467380096 (ISBN) ; Tavana, M. K ; Rehman, S ; Kriebel, F ; Shafique, M ; Ejlali, A ; Henkel, J ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling...
S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs
, Article 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip,, 29 June 2015 through 1 July 2015 ; June , 2015 , Page(s): 1 - 6 ; 9781467379427 (ISBN) ; Miremadi, S. G ; Janssen K ; DFG ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Data traversal in Network-on-Chips (NoCs) is threated by crosstalk fault seriously. Crosstalk fault leads to mutual influence between adjacent wires of NoCs and as a result endangers the reliability of data in NoCs. Crosstalk fault is strongly dependent on the transition patterns appearing on the wires of NoCs. Among these transitions, Triplet Opposite Directions (TODs) impose the worse crosstalk effects to the wires of NoCs. This paper proposes an efficient numerical-based coding mechanism called Summation-based-Subtracted-Added-Penultimate (S2AP) which alleviates crosstalk faults. This is done by completely removing TODs which are the main source of crosstalk faults in the channels of...
DiskAccel: Accelerating disk-based experiments by representative sampling
, Article Performance Evaluation Review, 15 June 2015 through 19 June 2015 ; Volume 43, Issue 1 , 2015 , Pages 297-308 ; 01635999 (ISSN) ; Asadi, H ; Sarbazi Azad, H ; Sharif University of Technology
Association for Computing Machinery
2015
Abstract
Disk traces are typically used to analyze real-life workloads and for replay-based evaluations. This approach benefits from capturing important details such as varying behavior patterns, bursty activity, and diurnal patterns of system activity, which are often missing from the behavior of workload synthesis tools. However, accurate capture of such details requires recording traces containing long durations of system activity, which are difficult to use for replay-based evaluation. One way of solving the problem of long storage trace duration is the use of disk simulators. While publicly available disk simulators can greatly accelerate experiments, they have not kept up with technological...
Design of mid-infrared ultra-wideband metallic absorber based on circuit theory
, Article Optics Communications ; Volume 381 , 2016 , Pages 309-313 ; 00304018 (ISSN) ; Abdollahramezani, S ; Farajollahi, S ; Khavasi, A ; Rejaei, B ; Sharif University of Technology
Elsevier B.V
2016
Abstract
An ultra-broadband absorber of light is proposed by using periodic array of ultra-thin metallic ribbons on top of a lossless quarter-wavelength dielectric spacer placed on a metallic reflector. We propose a fully analytical circuit model for the structure, and then the absorber is duly designed based on the impedance matching concept. As a result, normalized bandwidth of 99.5% is realized by the proposed absorbing structure in mid-infrared regime. Performing a numerical optimization algorithm, we could also reach to normalized bandwidth of 103%
Designing low power and durable digital blocks using shadow nanoelectromechanical relays
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 24, Issue 12 , 2016 , Pages 3489-3498 ; 10638210 (ISSN) ; Khaleghi, B ; Ienne, P ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy...