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reconfigurable-hardware
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Reducing the Energy Consumption of the Embedded Real-Time Systems with Reconfigurable Components
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
Over the Recent Decade, the embedded systems have expanded to include a wide variety of products, ranging from digital cameras, to medical systems, to Radar and telecommunication systems, to sensor networks. Engineers strive to create ever smaller and faster products, many of which, such as battery operated systems, have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Dynamic reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems....
Design of Reconfigurable Hardware Security Module Based on Network Protocol Detection
,
M.Sc. Thesis
Sharif University of Technology
;
Jahangir, Amir Hossein
(Supervisor)
Abstract
Nowadays, in the presence of different types of computer attacks and different methods of eavesdropping on network communications, nobody can deny the importance of cryptography. Hardware Security Modules that are specifically designed for this purpose are widely used as a fast and reliable tool for encrypting data in computer networks. In this project, using the common and well-known FPGA platform and by leveraging the reconfigurability feature of this platform and also by adding a network protocol detection module to the traditional architecture of Hardware Security Modules, a novel module has been designed and implemented that can encrypt and decrypt data in a communication network, at...
Accelerating Numerical Solution of Steady and Unsteady Equations Using FPGA
, Ph.D. Dissertation Sharif University of Technology ; Ebrahimi, Abbas (Supervisor)
Abstract
Nowadays one of the main challenges facing fluid dynamics simulations is the long duration of numerical calculations. The goal of this research is to use FPGAs (Field Programmable Gate Arrays) to accelerate fluid dynamics solutions. First, the ability of FPGAs in mathematical operations on floating point numbers is studied. Then, various fluid dynamics problems are implemented on the FPGA hardware, and each one is solved separately. Unsteady 1D Couette problem, 2D potential flow (Laplace equation), incompressible viscous fluid flow over a backward facing step, and compressible inviscid flow over a bump are some of the problems in question. FPGA is an integrated circuit containing a number of...
Wireless interfacing to cortical neural recording implants using 4-FSK modulation scheme
, Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016 March , 2016 , Pages 221-224 ; 9781509002467 (ISBN) ; Judy, M ; Molaei, H ; Sodagar, A. M ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
This paper used a 4-level frequency shift keying (4-FSK) modulation scheme to enhance the density of wireless data transfer from implantable biomedical microsystems to the outside world. Modeling and simulation of the wireless channel for 4-FSK modulation in the case of a neural recording implant has been done. To realize the 4-FSK scheme, the modulator and demodulator circuits are proposed, designed and simulated in a 0.18-μm CMOS process, and in the 174-216 MHz frequency band at a data rate of 13.5 Mbps. Operated using a 1.8 V supply voltage, the modulator circuit consumes a power of 7.8 μW
Water hammer in a horizontal rectangular conduit containing air-water two-phase slug flow
, Article Journal of Hydraulic Engineering ; Volume 142, Issue 3 , 2016 ; 07339429 (ISSN) ; Borghei, S. M ; Kabiri Samani, A ; Sharif University of Technology
American Society of Civil Engineers (ASCE)
2016
Abstract
The study of water hammer in air-water, two-phase flows in hydraulic structures such as pressurized pipelines and tunnels, siphons, culverts, and junctions is of great importance for design purposes. Water hammer if combined with a periodic slug flow would lead to severe periodic transient pressure fluctuations inside the conduit. Laboratory experiments have been conducted to investigate waterhammer pressure inside a horizontal rectangular conduit carrying a two-phase, air-water slug flow. Tests were performed in an experimental apparatus comprising a 6.8-m-long transparent pipeline 0.06 m wide and 0.1 m high. By rapidly closing a control gate at the end of the conduit, propagating pressure...
Ultra-Sharp Transmission Resonances in Periodic Arrays of Graphene Ribbons in TE Polarization
, Article Journal of Lightwave Technology ; Volume 34, Issue 3 , 2016 , Pages 1020-1024 ; 07338724 (ISSN) ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
When illuminated by TM polarized waves, periodic arrays of graphene ribbons are known to exhibit plasmonic resonances due to their dual inductive-capacitive nature. It is demonstrated here that even in TE polarization, resonances can be observed in these structure. These resonances, which are of nonplasmonic origin, are explained by means of a circuit model. It is shown that, for a certain frequency range, arrays of graphene ribbons have both capacitive and inductive properties, which lead to an ultra-sharp inductor-capacitor resonance. The banw idth of this resonance can be as narrow as ∼0.0002 nm at a wavelength of 630 nm. The resonance can also be viewed as the grating excitation of a TE...
Traffic-aware buffer reconfiguration in on-chip networks
, Article IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 5 October 2015 through 7 October 2015 ; Volume 2015-October , 2015 , Pages 201-206 ; 23248432 (ISSN) ; 9781467391405 (ISBN) ; Sarbazi-Azad, H ; Sharif University of Technology
IEEE Computer Society
2015
Abstract
Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,...
Towards dark silicon era in FPGAs using complementary hard logic design
, Article Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 ; Sept , 2014 , pp. 1 - 6 ; ISBN: 9783000446450 ; Khaleghi, B ; Ebrahimi, Z ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
Abstract
While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional...
Thermal and power aware task mapping on 3D Network on Chip
, Article Computers and Electrical Engineering ; Volume 51 , 2016 , Pages 157-167 ; 00457906 (ISSN) ; Mehdizadeh Amiraski, A ; Hessabi, S ; Sharif University of Technology
Elsevier Ltd
Abstract
High integration and increased elements density in 3D Network on Chip (NoC) will cause more energy consumption and high temperature on chip. By mapping those tasks that have data communication between them to near cores, the communication delay and therefore, power consumption will be reduced. In addition, mapping the tasks to cores that are near the heat sink, in such a way that the generated heat is distributed indiscriminately all over the chip, will decrease maximum chip temperature. In this paper, we propose a task mapping method based on fuzzy logic that aims to alleviate power and thermal problems in 3D-NoCs. In this method, the weight of task mapping factors can be changed according...
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs
, Article 26th International Conference on Field-Programmable Logic and Applications, FPL 2016, 29 August 2016 through 2 September 2016 ; 2016 ; 9782839918442 (ISBN) ; Omidi, B ; Amrouch, H ; Henkel, J ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration...
Smart mesoporous silica nanoparticles for controlled-release drug delivery
, Article Nanotechnology Reviews ; Volume 5, Issue 2 , 2016 , Pages 195-207 ; 21919089 (ISSN) ; Mirshekari, H ; Aliakbari, M ; Sahandi Zangabad, P ; Hamblin, M. R ; Sharif University of Technology
Walter de Gruyter GmbH
2016
Abstract
Stimuli-responsive controlled-release nanocarriers are promising vehicles for delivery of bioactive molecules that can minimize side effects and maximize efficiency. The release of the drug occurs when the nanocarrier is triggered by an internal or external stimulus. Mesoporous silica nanoparticles (MSN) can have drugs and bioactive cargos loaded into the high-capacity pores, and their release can be triggered by activation of a variety of stimulus-responsive molecular "gatekeepers" or "nanovalves." In this mini-review, we discuss the basic concepts of MSN in targeted drug-release systems and cover different stimulus-responsive gatekeepers. Internal stimuli include redox, enzymes, and pH,...
S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs
, Article 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip,, 29 June 2015 through 1 July 2015 ; June , 2015 , Page(s): 1 - 6 ; 9781467379427 (ISBN) ; Miremadi, S. G ; Janssen K ; DFG ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Data traversal in Network-on-Chips (NoCs) is threated by crosstalk fault seriously. Crosstalk fault leads to mutual influence between adjacent wires of NoCs and as a result endangers the reliability of data in NoCs. Crosstalk fault is strongly dependent on the transition patterns appearing on the wires of NoCs. Among these transitions, Triplet Opposite Directions (TODs) impose the worse crosstalk effects to the wires of NoCs. This paper proposes an efficient numerical-based coding mechanism called Summation-based-Subtracted-Added-Penultimate (S2AP) which alleviates crosstalk faults. This is done by completely removing TODs which are the main source of crosstalk faults in the channels of...
Reliability-aware design to suppress aging
, Article 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, 5 June 2016 through 9 June 2016 ; Volume 05-09 , June-2016 , 2016 ; 0738100X (ISSN); 9781450342360 (ISBN) ; Khaleghi, B ; Gerstlauerz, A ; Henkel, J ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this paper, we propose to bring aging awareness to EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on both threshold voltage (Vth) and carrier mobility (μ) of transistors. This is unlike state of the art which considers Vth only. We show how ignoring μ degradation leads to underestimating guard-bands by 19% on average. Our investigation revealed that the impact of aging is strongly dependent on the...
Reconfigurable multicast routing for Networks on Chip
, Article Microprocessors and Microsystems ; Volume 42 , 2016 , Pages 180-189 ; 01419331 (ISSN) ; Sarbazi Azad, H ; Khademzadeh, A ; Sharif University of Technology
Elsevier
Abstract
Several unicast and multicast routing protocols have been presented for MPSoCs. Multicast protocols in NoCs are used for cache coherency in distributed shared memory systems, replication, barrier synchronization, or clock synchronization. Unicast routing algorithms are not suitable for multicast, as they increase traffic, congestion and deadlock probability. Famous multicast schemes such as tree-based and path-based schemes have been proposed originally for multicomputers and recently adapted to NoCs. In this paper, we propose a switch tree-based multicast scheme, called STBA. This method supports tree construction with a minimum number of routers. Our evaluation results reveal that, for...
Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology
, Article Microprocessors and Microsystems ; April , 2016 ; 01419331 (ISSN) ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
Elsevier
2016
Abstract
Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the...
Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology
, Article Microprocessors and Microsystems ; Volume 46 , 2016 , Pages 122-135 ; 01419331 (ISSN) ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
Elsevier B.V
2016
Abstract
Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the...
Potential of light-harvesting of bacteriorhodopsin co-sensitized with green fluorescence protein: A new insight into bioenergy application
, Article Biomass and Bioenergy ; Volume 87 , 2016 , Pages 35-38 ; 09619534 (ISSN) ; Janfaza, S ; Zeinoddini, M ; Sharif University of Technology
Elsevier Ltd
2016
Abstract
Herein we report for the first time on efficient and environmentally friendly bioenergy production from bacteriorhodopsin (bR) and green florescent protein (GFP) as co-sensitizers. bR as a transmembrane protein, acts like a light-driven proton pump in Halobacterium salinarum, converting light energy into a proton gradient. Employing GFP beside bR can enhance the photo-bioenergy production efficiency in two aspects: GFP can increase short circuit current by improvement in light absorption either by extending the sensitizingspectrumor making fluorescence in absorption region of bR. It can also enhance open circuit voltage more than 150 mV by improvement in photoelectrode converging and...
Performance analysis of carrier-less modulation schemes for wireless nanosensor networks
, Article 15th IEEE International Conference on Nanotechnology, 27 July 2015 through 30 July 2015 ; 2015 , Pages 45-50 ; 9781467381550 (ISBN) ; Hassan, M ; Chou, C. T ; Bayat, S ; Nanotechnology Council ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
Wireless Nano-scale Sensor Networks (WNSNs) are very simple and energy restricted networks that operate over terahertz band ranging from 0.1-10 THz, which faces significant molecular absorption noise and attenuation. Given these challenges, reliability, energy efficiency, and simplicity constitute the main criteria in designing communication protocols for WNSNs. Due to its simplicity and energy efficiency, carrier-less pulse based modulation is considered the best candidate for WNSNs. In this paper, we compare the performance of four different carrier-less modulations, PAM, OOK, PPM, and BPSK, in the context of WNSNs operating within the terahertz band. Our study shows that although BPSK is...
PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era
, Article IEEE Transactions on Computers ; Volume 66, Issue 6 , 2017 , Pages 982-995 ; 00189340 (ISSN) ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2017
Abstract
Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of...
Open-circuit switch fault tolerant wind energy conversion system based on six/five-leg reconfigurable converter
, Article Electric Power Systems Research ; Volume 137 , 2016 , Pages 104-112 ; 03787796 (ISSN) ; Saadate, S ; Poure, P ; Zolghadri, M ; Sharif University of Technology
Elsevier Ltd
2016
Abstract
In this paper, an FPGA-controlled fault tolerant back-to-back converter for DFIG-based wind energy conversion application is studied. Before an open-circuit failure in one of the semiconductors, the fault tolerant converter operates as a conventional back-to-back six-leg one. After the fault occurrence in one of the switches, the converter will continue its operation with the remaining five healthy legs. Design, implementation, simulation and experimental verification of a reconfigurable control strategy for the fault tolerant six/five leg converter used in wind energy conversion are discussed. The proposed reconfigurable control strategy allows the uninterrupted operation of the converter...