Sharif Digital Repository

Providing Quality-of-Service (QoS) in many-core network-on-chip (NoC) platforms is critical due to the high level of resource sharing in such systems. This article presents a hard-built Equality-of-Service (EoS) and Differential-Service (DS) as subsets of QoS in NoC using weighted round-robin arbitration policy. In the proposed technique, packets can be injected with variable initial weights. An enhanced dynamic weight incremental technique is proposed that automatically increases the weights according to the contention degree that packets face along their paths. The proposed technique provides EoS for all packets that are injected with equal initial weights. Furthermore, the router's input... 

Optical networks-on-chip are introduced as an alternative for electrical interconnects in many-core systems, due to their low delay and power consumptions, as well as their high bandwidths. Despite these advantages, physical characteristics of the photonic components are highly sensitive to thermal variations, which results in optical data misrouting through the optical networks at the presence of temperature fluctuation. In this paper, we propose a thermally-resilient all-optical communication approach which improves reliability, as well as performance of the optical networks. For this purpose, we take advantages of auxiliary waveguides and a novel wavelength assignment approach to avoid... 

Due to high aggregate idle time of Networks-on-Chip (NoCs) routers in practical applications, power-gating techniques have been proposed to combat the ever-increasing ratio of static power. Nevertheless, the sporadic packet arrivals compromise the effectiveness of power-gating by incurring significant latency and energy overhead. In this paper, we propose a Scalable Pivot-based On/Off Gating Engine (SPONGE) which efficiently manages power-gating decisions and routing mechanism by adaptively selecting a small set of powered-on columns of routers and keeping the others in power-gated state. To this end, a router architecture augmented with a novel routing algorithm is proposed in which a... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

Server workloads benefit from execution on many-core processors due to their massive request-level parallelism. A key characteristic of server workloads is the large instruction footprints. While a shared last-level cache (LLC) captures the footprints, it necessitates a low-latency network-on-chip (NOC) to minimize the core stall time on accesses serviced by the LLC. As strict quality-of-service requirements preclude the use of lean cores in server processors, we observe that even state-of-the-art single-cycle multi-hop NOCs are far from ideal because they impose significant NOC-induced delays on the LLC access latency, and diminish performance. Most of the NOC delay is due to per-hop... 

With technology scaling, crosstalk fault has become a serious problem in reliable data transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on transition patterns appearing on the wires of NoC channels. Among these patterns, Triplet Opposite Direction (TOD) imposes the worst crosstalk effects. Crosstalk Avoidance Codes (CACs) are the overhead-efficient mechanisms to tackle TODs. The main problem of CACs is their high imposed overheads to NoC routers. To solve this problem, this paper proposes an overhead-efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits... 

With the growing number of cores, high-performance systems face power challenges due to dominating communication power. Thus, attaining energy efficient high-bandwidth inter-core communication nominates photonic network-on chip as the most promising interconnection paradigm. Although photonic networks pave the way for extremely higher performance communications, their intrinsic susceptibility to thermal fluctuations intimidates reliability of system. This necessitates the development of methodologies to analyze and model thermal effects on network behavior. In this paper, we model temperature fluctuations of optical chips and analyze photonic networks in a holistic approach. We present a... 

The severity of timing delay in the communication channels of Network on Chip (NoC) depends on the transition patterns appearing on the wires. An analytical model can estimate the timing delay in NoC channels in the presence of crosstalk faults. However, recently proposed analytical model does not have enough accuracy and is based on 3-wire delay model. In this paper, an Accurate Crosstalk Model (ACM) based on 5-wire delay model is proposed to estimate the delay of communication channels in the presence of crosstalk faults. ACM is more accurate due to considering more wires in the delay model and also considering the overlaps between locations of transition patterns  

Vehicular Ad-hoc Networks (VANET) has attracted a great deal of attention during the last decade. This type of wireless network is predicted to play a key role in future automotive innovation. VANET as a foundation for Intelligent Transportation System (ITS) promises many improvements in terms of safety, resource efficiency and passenger assistance services. Among these three main categories, safety applications are the most important ones because they deal with the lives of large numbers of people who drive every day. Safety applications are classified as real-time applications; they must act within a certain period of time, otherwise their implementation will be worthless. As a result,... 

With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Powergating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overhead of the packets that encounter powered-off... 

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we... 

Key pre-distribution algorithms have recently emerged as efficient alternatives of key management in today's secure communications landscape. Secure routing techniques using key pre-distribution algorithms require special algorithms capable of finding optimal secure overlay paths. To the best of our knowledge, the literature of key pre-distribution systems is still facing a major void in proposing optimal overlay routing algorithms. In the literature work, traditional routing algorithms are typically used twice to find a NETWORK layer path from the source node to the destination and then to find required cryptographic paths. In this paper, we model the problem of secure routing using... 

This paper proposes an efficient mechanism that mitigates crosstalk faults in Network-on-Chips (NoCs). This is done by using a Packet Manipulating mechanism called PAM for reliable data transfer of NoCs. PAM investigates the transitions of a packet to minimize the forbidden transition patterns appearing during the flit traversal in NoCs. To do this, the content of a packet is manipulated using three different manipulating mechanisms. In other words, PAM manipulates the content of packet in three manipulating modes including: vertical, horizontal and diagonal modes. Then, comparing the transitions of these manipulating mechanisms, a packet with minimum numbers of transitions is selected to be... 

Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,... 

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

Data traversal in Network-on-Chips (NoCs) is threated by crosstalk fault seriously. Crosstalk fault leads to mutual influence between adjacent wires of NoCs and as a result endangers the reliability of data in NoCs. Crosstalk fault is strongly dependent on the transition patterns appearing on the wires of NoCs. Among these transitions, Triplet Opposite Directions (TODs) impose the worse crosstalk effects to the wires of NoCs. This paper proposes an efficient numerical-based coding mechanism called Summation-based-Subtracted-Added-Penultimate (S2AP) which alleviates crosstalk faults. This is done by completely removing TODs which are the main source of crosstalk faults in the channels of... 

Abstract Network on Chip (NoC) is an appropriate and scalable solution for today's System on Chips (SoCs) with the high communication demands. Application specific NoCs is preferable since they can be customized to optimize all requirements of the specific applications. This paper presents an OPtimization technique for Application specifIC NoCs (OPAIC), which aims not only to decrease the energy consumption but also to improve the area of NoCs. OPAIC is composed of three stages to find the optimum NoC; in the first stage, it uses a linearized form of a Quadratic Assignment Problem (QAP) to map tasks on cores to minimize the energy. In the second stage, a Mixed Integer Linear Problem (MILP)... 

This paper presents a reconfigurable network-on-chip (NoC) for many-core chip multiprocessors (CMPs) in the dark silicon era, where a considerable part of high-end chips cannot be powered up due to the power and bandwidth walls. Core specialization, which trades off the cheaper silicon area with energy-efficiency, is a promising solution to the dark silicon challenge. This approach integrates a selection of many diverse application-specific cores into a single many-core chip. Each application then activates those cores that best match its processing requirements. Since active cores may not always form a contiguous active region in the chip, such a partially active many-core CMP requires some... 

Mobile Ad-hoc Networks (MANETs) are forming dynamically by joining or leaving the nodes into/from the network without any fix infrastructure. It is also possible that each mobile node act as a host or router. This kind of wireless network is prone to various security threats or attacks due to its unique characteristics like dynamic topology, open medium, lack of central monitoring, etc. So security is a vital scope in MANET to protect communication between mobile nodes. Ad-hoc On-demand Distance Vector (AODV) is one of the on-demand reactive routing protocols in MANET that initially was improved without considering security protection. Significant attempts have been done to secure AODV... 

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our...