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transient-faults
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Transient Fault Detection in Embedded Processors using Built In Self-Test (BIST) Facilities
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghassem (Supervisor)
Abstract
Ever increasing applications of embedded systems have motivated designers to pay special atten-tion to the design requirements of such systems. Among embedded applications, safety-critical sys-tems have high reliability requirements as failures in such systems may endanger human life or re-sult in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. Reducing feature size, power supply voltage and also increasing operating frequency have increased the occurance rate of transient faults in such processors. Built in Self-Test facilities available in many of embedded systems forms about 70% of total cost in...
Low-cost scan-chain-based technique to recover multiple errors in TMR systems
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 8 , 2013 , Pages 1454-1468 ; 10638210 (ISSN) ; Miremadi, S. G ; Asadi, H ; Fazeli, M ; Sharif University of Technology
2013
Abstract
In this paper, we present a scan-chain-based multiple error recovery technique for triple modular redundancy (TMR) systems (SMERTMR). The proposed technique reuses scan-chain flip-flops fabricated for testability purposes to detect and correct faulty modules in the presence of single or multiple transient faults. In the proposed technique, the manifested errors are detected at the modules' outputs, while the latent faults are detected by comparing the internal states of the TMR modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules. In case of detecting a permanent fault, the system is degraded to a...
An FSM-based monitoring technique to differentiate between follow-up and original errors in safety-critical distributed embedded systems
, Article Microelectronics Journal ; Volume 42, Issue 6 , June , 2011 , Pages 863-873 ; 00262692 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2011
Abstract
Nowadays, distributed embedded systems are employed in many safety-critical applications such as X-by-Wire. These systems are composed of several nodes interconnected by a network. Studies show that a transient fault in the communication controller of a network node can lead to errors in the fault site node (called original errors) and/or in the neighbor nodes (called follow-up errors). The communication controller of a network node can be halted due to an error, which may be a follow-up error. In this situation, a follow-up error leads to halt the correct operation of a fault-free controller while the fault site node, i.e. the faulty controller, still continues its operation. In this paper,...
An extended component-based reliability model for protective systems to determine routine test schedule
, Article Turkish Journal of Electrical Engineering and Computer Sciences ; Volume 19, Issue 2 , March , 2011 , Pages 303-315 ; 13000632 (ISSN) ; Firuzabad, M. F ; Ozdemir, A ; Sharif University of Technology
2011
Abstract
This paper presents a novel approach for evaluating the reliability of protective systems taking into account its components reliability. In this paper, a previously proposed extended model is used for a directional over- current scheme. In the extended model, the impacts of individual protective components are taken into account. An optimum routine test schedule is determined for each protective component as a separate unit. A comparison is made to show that the proposed approach has excellence over conventional routine test inspections. Impacts of factors such as circuit breaker inadvertent opening, required time for performing routine test inspections, human mistakes and self-checking and...
Feature specific control flow checking in COTS-based embedded systems
, Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 58-63 ; 9780769540900 (ISBN) ; Miremadi, S.G ; IARIA ; Sharif University of Technology
2010
Abstract
While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is...
Classification of activated faults in the flexray-based networks
, Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 26, Issue 5 , October , 2010 , Pages 535-547 ; 09238174 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
Abstract
FlexRay communication protocol is expected to become the de-facto standard for distributed safety-critical systems. This paper classifies the effects of transient single bit-flip fault injections into the FlexRay communication controller. In this protocol, when an injected fault is activated, this may result in one or more error types, i.e.: Boundary violation, Conflict, Content, Freeze, Synchronization, Syntax, and Invalid frame. To study the activated faults, a FlexRay bus network, composed of four nodes, was modeled by Verilog HDL; and a total of 135,600 transient faults was injected in only one node, called the target node. The results show that only 9,342 of the faults (about 6.9%) were...
A novel routine test schedule for protective systems using an extended component-based reliability model
, Article ELECO 2009 - 6th International Conference on Electrical and Electronics Engineering14 December 2009 ; 2009 , Pages I97-I102 ; 9789944898188 (ISBN) ; Fotuhi Firuzabad, M ; Sharif University of Technology
Abstract
This paper presents a novel approach for evaluating the reliability of protective systems taking into account its components reliability. In this paper, a previously proposed extended model is used for Directional Overcurrent scheme. In the extended model, the impacts of individual protective components are taken into account. An optimum routine test schedule is determined for each protective component as a separate unit. A comparison is made to show that the proposed approach has excellence over conventional routine test inspections. Impacts of factors such as circuit breaker inadvertent opening, required time for performing routine test inspections, human mistakes and self-checking and...
Improvement of fault detection in wireless sensor networks
, Article 2009 Second ISECS International Colloquium on Computing, Communication, Control, and Management, CCCM 2009, Sanya, 8 August 2009 through 9 August 2009 ; Volume 4 , 2009 , Pages 644-646 ; 9781424442461 (ISBN) ; Barati, A ; Movaghar, A ; Yangzhou University; Guangdong University of Business Studies; Wuhan Institute of Technology; IEEE SMC TC on Education Technology and Training; IEEE Technology Management Council ; Sharif University of Technology
2009
Abstract
This paper presents a centralized fault detection algorithm for wireless sensor networks. Faulty sensor nodes are identified based on comparisons between neighboring nodes and own central node and dissemination of the decision made at each node. RNS system is used to tolerate transient faults in sensing and communication. In this system, arithmetic operations act on residues - reminder of dividing original number in several definite modules - in parallel. Consequently computations on these residues which are smaller than the original number are performed, so speed up arithmetic and decreased power consumption is achieved. ©2009 IEEE
A low-cost on-line monitoring mechanism for the flexray communication protocol
, Article Proceedings - 2009 4th Latin-American Symposium on Dependable Computing, LADC 2009, 1 September 2009 through 4 September 2009, Joao Pessoa ; 2009 , Pages 111-118 ; 9780769537603 (ISBN) ; Miremadi, G ; Sharif University of Technology
2009
Abstract
Nowadays, communication protocols are used in safety-critical automotive applications. In these applications, fault tolerance is a main requirement and the existence of single points of failure is a serious threat to system failures. Among the communication protocols, FlexRay is expected to become the communication backbone for future automotive systems. In this paper, we identify single points of failure in the FlexRay protocol by injecting a total of 135,600 single-bit transient faults into all accessible registers of the FlexRay communication controller. The results showed that about 1.2% of all injected faults caused the controller to freeze immediately. Based on these results and...
A low-cost fault-tolerant technique for carry look-ahead adder
, Article 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009, Sesimbra-Lisbon, 24 June 2009 through 26 June 2009 ; 2009 , Pages 217-222 ; 9781424445950 (ISBN) ; Sedaghat, Y ; Miremadi, G ; Ejlali, A. R ; Sharif University of Technology
2009
Abstract
This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques. © 2009 IEEE
Categorizing and analysis of activated faults in the flexray communication controller registers
, Article Proceedings of the 14th IEEE European Test Symposium, ETS 2009, 25 May 2009 through 29 May 2009, Sevilla ; 2009 , Pages 121-126 ; 9780769537030 (ISBN) ; Miremadi, G ; Sharif University of Technology
2009
Abstract
FlexRay communication protocol is expected becoming the de-facto standard for distributed safetycritical systems. In this paper, transient single bit-flip faults were injected into the FlexRay communication controller to categorize and analyze the activatedfaults. In this protocol, an activated fault results in one or more error types which are Boundary violation, Conflict, Content, Freeze, Synchronization, and Syntax. To study the activated faults, a FlexRay bus network, composed of four nodes, was modeled by Verilog HDL; and a total of 135,600 transient faults were injected in only one node, where 9,342 (6.9%) of the faults were activated. The results show that the Synchronization error is...
A high speed and low cost error correction technique for the carry select adder
, Article International Conference on Availability, Reliability and Security, ARES 2009, Fukuoka, Fukuoka Prefecture, 16 March 2009 through 19 March 2009 ; 2009 , Pages 635-640 ; 9780769535647 (ISBN) ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
2009
Abstract
In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder. The synthesized results show that applying this novel error correction technique to a CSA with error detection technique results in up to 18.4%, 3.1% and 14.9%, increase in power consumption, delay and area respectively. © 2009 IEEE
A unified approach to detect and distinguish hardware trojans and faults in sram-based fpgas
, Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 35, Issue 2 , 2019 , Pages 201-214 ; 09238174 (ISSN) ; Bayat Sarmadi, S ; Pooyan, F ; Asadi, H ; Sharif University of Technology
Springer New York LLC
2019
Abstract
In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low design cost and short time-to-market. Besides their vulnerability to hardware Trojan attacks, SRAM-based reconfigurable devices are also significantly susceptible to faults originated by particle strikes. There have been various methods to mitigate either hardware Trojan attacks or faults. To our knowledge, however, no method has been presented that can integrate detecting, distinguishing, and mitigating faults and Trojans. In this paper, we...
An Improved aggregated model of residential air conditioners for FIDVR studies
, Article IEEE Transactions on Power Systems ; Volume 35, Issue 2 , 2020 , Pages 909-919 ; Saber, H ; Farzin, N ; Karimi, M. R ; Hashemi, S. M ; Agheli, A ; Ayoubzadeh, H ; Ehsan, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2020
Abstract
Stalling of residential air conditioners (RACs) following a transient fault can delay the voltage recovery ranging from 3 to 20 seconds. This phenomenon is referred to as fault-induced delayed voltage recovery (FIDVR). Several aggregated RAC models have been presented to replicate the actual FIDVR events. However, they usually have two main drawbacks as: i) considering independent stalling voltage and stalling time for all RACs, ii) resulting in only two ultimate modes; either 100% stalled or 100% normal running. This paper amends the abovementioned shortcomings by proposing a simple and effective performance-based RAC model. The proposed model utilizes a simple explicit relation between the...
A comprehensive analysis on the resilience of adiabatic logic families against transient faults
, Article Integration ; Volume 72 , May , 2020 , Pages 183-193 ; Safaei, B ; Ejlali, A ; Sharif University of Technology
Elsevier B.V
2020
Abstract
With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of...
A power efficient approach to fault-tolerant register file design
, Article Proceedings of the IEEE International Frequency Control Symposium and Exposition, 4 January 2008 through 8 January 2008, Hyderabad ; 2008 , Pages 21-26 ; 0769530834 (ISBN); 9780769530833 (ISBN) ; Miremadi, S. G ; Fazeli, M ; Sharif University of Technology
2008
Abstract
Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an...
Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor
, Article ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings, 4 March 2008 through 7 March 2008, Barcelona ; 2008 , Pages 648-652 ; 0769531024 (ISBN); 9780769531021 (ISBN) ; Shokrolah Shirazi, M ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core described at the RTL model. A comparison of the effects of faults on the various parts of the CPU including the pipeline's registers, the CPU component such as the register file, the control unit, and the ALU, and the data and address buses is done. It is shown that about 30%, 40% and 27% of injected faults terminated in address, data, and control errors respectively. About 28% of all injected faults resulted in failures. © 2008 IEEE
A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic
, Article 20th International Conference on Microelectronics, ICM'08, Sharjah, 14 December 2008 through 17 December 2008 ; January , 2008 , Pages 470-473 ; 9781424423705 (ISBN) ; Tabkhi, H ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
2008
Abstract
The increasing rate of transient faults necessitates the use of on-chip fault-tolerant techniques in embedded microprocessors. Performance overhead is a challenging problem in on-chip fault-tolerant techniques used in the random logic of the embedded microprocessors. This paper presents a signature-based error detection and roll-back recovery technique for the control logic with much lower performance overhead as compared to many previous techniques. The low performance overhead is achieved by eliminating the fault masking overhead cycles in the previous techniques. The performance overhead is analytically studied, and the analytical results recommend at which fault rate the use of the...
Survivability analysis of wireless sensor network with transient faults
, Article 2008 International Conference on Computational Intelligence for Modelling Control and Automation, CIMCA 2008, Vienna, 10 December 2008 through 12 December 2008 ; 2008 , Pages 975-980 ; 9780769535142 (ISBN) ; Jahangir, A. H ; Taghikhaki, Z ; Sharif University of Technology
2008
Abstract
To the best knowledge of us, survivability for WSN has never been studied considering failure affects on network. We perceive the network survivability as a composite measure consisting of both network failure duration and failure impact on the network. In this paper we will study network survivability in unstably state: in this state, network is affected by the failures that occur temporarily and instantly also may occur several times. In other words, the main characteristics of these failures are their frequency and being temporary. In this paper we will propose a survivability model for network in unstable state that is based on network availability. This availability model, presents...
Error detection enhancement in PowerPC architecture-based embedded processors
, Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 24, Issue 1-3 , 2008 , Pages 21-33 ; 09238174 (ISSN) ; Farivar, R ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer...