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A 90 nm-CMOS IR-UWB BPSK transmitter with spectrum tunability to improve peaceful UWB-narrowband coexistence
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, issue. 6 , January , 2014 , p. 1836-1848 ; 15498328 ; Fotowat-Ahmady, A ; Nezhad, A. Z ; Serdijn, W. A ; Sharif University of Technology
Abstract
A new ultra wideband (UWB) pulse generator covering a-10 dB bandwidth of 2.4-4.6 GHz with a tunable center frequency of 5-5.6 GHz to mitigate coexistence issues of impulse radio UWB (IR-UWB) systems and IEEE802.11.a WLAN or other narrowband (NB) systems in 90 nm-CMOS technology is proposed. The UWB pulse is generated based on frequency up-conversion of the first derivative of the Gaussian pulse, which creates an adjustable null in the frequency spectrum. Simulation results show that employing the proposed pulse generator mitigates the mutual interference between UWB and WLAN systems, significantly. The proposed transmitter consists of a low frequency signal generator, an LC oscillator and a...
An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding
, Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 797-800 ; 02714310 (ISSN) ; 9781467357609 (ISBN) ; Mahdavi, M ; Shabany, M ; Sharif University of Technology
2013
Abstract
Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design...
A UHF-RFID transceiver with a blocker-canceller feedback and 30 dBm output power
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 11 , 2013 , Pages 3043-3054 ; 15498328 (ISSN) ; Rezaei, V. D ; Bakhtiar, M. S ; Sharif University of Technology
2013
Abstract
A single chip UHF-RFID transceiver front-end is presented. The chip was designed according to EPCglobal Class-1 Gen-2 and supports both ETSI and FCC requirements. The receiver front end is capable of rejecting self-jammers as large as 10 dBm with the aid of a feedback loop. The stability and the robustness of the loop and other system requirements are studied. A 30 dBm class-AB power amplifier (PA) with 28% PAE is also integrated on the chip. The pseudo differential architecture of the PA greatly reduces the injection of the signal into the substrate. A simple model is used to estimate the effect of the substrate noise injection by the PA on the receiving circuit modules and design guides...
A layout-based approach for multiple event transient analysis
, Article Proceedings - Design Automation Conference ; 2013 ; 0738100X (ISSN) ; 9781450320719 (ISBN) ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
2013
Abstract
With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout- based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is pro- posed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER....
A 4-Bit, 1.6 GS/s low power flash ADC, based on offset calibration and segmentation
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 9 , 2013 , Pages 2285-2297 ; 15498328 (ISSN) ; Sharifkhani, M ; Sadughi, S ; Sharif University of Technology
2013
Abstract
A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after...
A novel low power architecture for DLL-based frequency synthesizers
, Article Circuits, Systems, and Signal Processing ; Volume 32, Issue 2 , 2013 , Pages 781-801 ; 0278081X (ISSN) ; Sharif University of Technology
2013
Abstract
This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is...
A low complexity architecture for the cell search applied to the LTE systems
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; Dec , 2012 , Pages 300-303 ; 9781467312615 (ISBN) ; Sharifan, G ; Amini, Y ; Shabany, M ; Sharif University of Technology
2012
Abstract
Cell search is a crucial process in the synchronization procedure for the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) system. In this paper, a high-speed, low-complexity and reliable architecture is proposed for both steps of cell search: sector ID and cell ID group detection. For the sector ID detection, two novel methods, sign-bit reduction and wise resource sharing, are proposed. In addition, for the cell ID group detection, we proposed an algorithm based on the Maximum Likelihood Sequence Detection (MLSD) called 'sign-bit MLSD'. Simulations show that the proposed methods result in more than 90% reduction in area compared to the state-of-the-art. We designed and...
A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18μm CMOS
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Seville, Seville, 9 December 2012 through 12 December 2012 ; 2012 , Pages 157-160 ; 9781467312615 (ISBN) ; Fotowat Ahmady, A ; Jenabi, M ; Sharif University of Technology
2012
Abstract
A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using...
A UHF micro-power CMOS rectifier using a novel diode connected CMOS transistor for micro-sensor and RFID applications
, Article International Conference on Electronic Devices, Systems, and Applications ; 2012 , Pages 234-238 ; 21592047 (ISSN) ; 9781467321631 (ISBN) ; Hamidon, M. N ; Khoddam, M ; Najafi, V ; Sharif University of Technology
2012
Abstract
The design strategy and efficiency optimization of UHF micro-power rectifiers using a novel diode connected MOS transistor is presented. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduce the threshold voltage and leakage current in compare to conventional diode connected transistors. Using the proposed diode in typical rectifiers makes a significant improvement in output voltage and current therefore the efficiency is increased comparing to the same rectifier architectures using conventional diodes. Also a design procedure for efficiency optimization is presented and a superposition method is used to optimize the performance of multiple output...
New operational transconductance amplifiers using current boosting
, Article Midwest Symposium on Circuits and Systems ; 2012 , Pages 109-112 ; 15483746 (ISSN) ; 9781467325264 (ISBN) ; Lazarjan, V. K ; HajSadeghi, K ; Sharif University of Technology
2012
Abstract
New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method
Down-conversion self-oscillating mixer by using CMOS technology
, Article Proceedings - 2012 IEEE 8th International Colloquium on Signal Processing and Its Applications, CSPA 2012 ; 2012 , Pages 33-36 ; 9781467309615 (ISBN) ; Zahedi, A ; Sabaghi, M ; Ameri, S. R. H ; Niyakan, M ; Sharif University of Technology
2012
Abstract
In this paper a self-oscillating mixer is presented fundamental signal generated by the oscillator subcircuit in the mixing process. The oscillator core consumes 3mA of current from a 1.8 V DC supply and results in an output power of -0.867 dBm per oscillator, and a measured phase noise of -91, -102 and -108 dBc/Hz at 100 KHz, 600 KHz and 1 MHz from the carrier, respectively. In the mixing process the proposed mixer achieved IIP3 of 0 dBm with conversation gain of 1.93 dB. The circuit was designed and simulated in 0.18-μm CMOS technology by ADS2010
Wideband LNA using active inductor with multiple feed-forward noise reduction paths
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 4 , 2012 , Pages 1069-1078 ; 00189480 (ISSN) ; Sharif Bakhtiar, M ; Sharif University of Technology
2012
Abstract
In this paper, an area-efficient LNA with on-chip input matching circuit utilizing an active inductor is presented. The active inductor is implemented based on the gyrator structure and its noise is improved by employing a feed-forward path (FFP). The overall low-noise performance of the LNA is achieved by cancelling the inductor noise through an additional FFP. It is shown that the proposed LNA circuit is capable of achieving low-noise performance with wideband tuning at the input in a small die area. A 0.32- to 1-GHz LNA has been designed and fabricated in a standard 0.18-μm CMOS technology. The LNA occupies a die area of less than 0.1 mm 2. The measured results show noise figure of...
An efficient architecture for Sequential Monte Carlo receivers in wireless flat-fading channels
, Article Journal of Signal Processing Systems ; Volume 68, Issue 3 , 2012 , Pages 303-315 ; 19398018 (ISSN) ; Sharif University of Technology
Springer New York LLC
2012
Abstract
A pipelined architecture is developed for a Sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The promising feature of the proposed SMC receiver is achieving the near-bound performance in fading channels without using any decision feedback, training or pilot symbols. The proposed architecture exploits the parallelism intrinsic to the algorithm and consists of three blocks, i.e., the SMC core, weight calculator, and resampler. Hardware efficient/parallel architectures for each functional block including the resampling block is developed. The novel feature of the proposed architecture is that makes the execution time of the resampling independent...
A low-power current reuse CMOS RF front-end for GPS applications
, Article 2011 IEEE International RF and Microwave Conference, RFM 2011 - Proceedings, 12 December 2011 through 14 December 2011, Seremban ; 2011 , Pages 416-419 ; 9781457716294 (ISBN) ; Fotowat Ahmady, A ; Sharif University of Technology
Abstract
A very low-power RF front-end based on a new current reuse QLMV cell (Quadrature VCO-LNA-Mixer) is proposed for GPS applications. The front-end, designed in 0.18μm CMOS technology, provides improved performance characteristics while consuming only 1 mA current. Simulation results are presented and compared with recently published works in the field
Single event upset immune latch circuit design using C-element
, Article Proceedings of International Conference on ASIC, 25 October 2011 through 28 October 2011, Xiamen ; 2011 , Pages 252-255 ; 21627541 (ISSN) ; 9781612841908 (ISBN) ; Tabandeh, M ; Sharif University of Technology
2011
Abstract
Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in...
New configuration memory cells for FPGA in nano-scaled CMOS technology
, Article Microelectronics Journal ; Volume 42, Issue 11 , 2011 , Pages 1187-1207 ; 00262692 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2011
Abstract
In nano-scaled CMOS technology, the reduction of soft error rate and leakage current are the most important challenges in designing Field Programmable Gate Arrays (FPGA). To overcome these challenges, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents three new low-leakage and hardened configuration memory cells for nano-scaled CMOS technology. These cells are completely hardened when zeros are stored in the cells and cannot flip from particle strikes at the sensitive cell nodes. These cells retain their data with...
Ultra high-throughput architectures for hard-output MIMO detectors in the complex domain
, Article Midwest Symposium on Circuits and Systems, 7 August 2011 through 10 August 2011l ; August , 2011 ; 15483746 (ISSN) ; 9781612848570 (ISBN) ; Shabany, M ; Sharif University of Technology
2011
Abstract
In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA...
A 6-bit active digital phase shifter
, Article IEICE Electronics Express ; Volume 8, Issue 3 , 2011 , Pages 121-128 ; 13492543 (ISSN) ; Atarodi, M ; Sharif University of Technology
2011
Abstract
This paper presents the design of a 6-bit active digital phase shifter in 0.18-μm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3±0.9 dBm at 3.5 GHz for overall phase states
A fully analog calibration technique for phase and gain mismatches in image-reject receivers
, Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 5 , May , 2015 , Pages 823-835 ; 14348411 (ISSN) ; Kananian, S ; Fotowat Ahmady, A ; Sharif University of Technology
Elsevier GmbH
2015
Abstract
A systematic approach to I/Q mismatch calibration in image-reject receivers is presented in this paper. A new error detection algorithm is proposed, which automatically calibrates for phase and gain mismatches limiting the performance of image-reject receivers. A dual-loop feedback is employed which looks for the minimum phase/gain error using a 2-dimensional analog-based search algorithm and then finds the minimum value for the error. An experimental CMOS prototype RF front-end for cognitive radio applications operating at 400-800 MHz is proposed and simulated in the 0.18 μm CMOS technology, achieving an image rejection ratio (IRR) better than 55-dB in post-layout simulation. The...
A compact 8-bit AES crypto-processor
, Article 2nd International Conference on Computer and Network Technology, ICCNT 2010, 232010 through 25 April 2010 ; April , 2010 , Pages 71-75 ; 9780769540429 (ISBN) ; Attarzadeh, H ; Sharifkhani, M ; Sharif University of Technology
2010
Abstract
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far