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cmos-technologies
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Design and Implementation of Local Interconnect Network (LIN)Transceiver in High Voltage BCD 0.18 um
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Faez, Ramin (Supervisor)
Abstract
In this study, a Local Interconnect Network (LIN) transceiver was designed and implemented. This chip contains transmitter, receiver, low power receiver, digital control unit, oscillator, voltage regulator, high voltage switch, temperature sensor and battery voltage detector. The main focus on this study was on designing transmitter,receiver, low power receiver and temperature sensor. Through designing of this chip, in addition to functional and physical layer specification that mentioned in ISO 17987, electromagnetic compatibility specifications have been considered significantly.The designed chip with slope control and wave shaping of BUS signal has excellent radiated emission performance....
Design of A Digitally Controlled Bias Chip For A Transceiver
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Sheikhaei, Samad (Supervisor)
Abstract
Advances in IC fabrication makes possible have systems on chips. In this thesis we have designed and fabricated a digitally controlled bias chip for a transceiver which can be programmed by its digital interface. In this thesis, briefly we review basics of voltage regulators and methods for controlling them. Then we introduce high voltage 0.18um CMOS technology. In this thesis, we describe the requirements of a specific transceiver and present a system to overcome these requirements. This system has positive, negative and internal regulators, a five-bit analog to digital converter, temperature sensors, power amplifier controller and digital serial interface. In this thesis, we present a...
A subthreshold symmetric SRAM cell with high read stability
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Vol. 61, issue. 1 , Jan , 2014 , p. 26-30 ; 15497747 ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition,...
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
, Article Integration, the VLSI Journal ; Volume 46, Issue 4 , September , 2013 , Pages 413-426 ; 01679260 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2013
Abstract
As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When...
A low-latency low-power QR-decomposition ASIC implementation in 0.13 μm CMOS
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 2 , 2013 , Pages 327-340 ; 15498328 (ISSN) ; Patel, D ; Gulak, P. G ; Sharif University of Technology
2013
Abstract
This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip,...
A VLSI architecture for multiple antenna eigenvalue-based spectrum sensing
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; December , 2012 , Pages 153-156 ; 9781467312615 (ISBN) ; Shabany, M ; Sharif University of Technology
2012
Abstract
An Eigenvalue-based detection (EBD) scheme, is proposed as an efficient method to overcome the noise uncertainty and the SNR wall problem in conventional energy detection (ED) schemes. Despite remarkable efforts made to analyze the EBD performance, a VLSI implementation is missing in literature. In this paper, a new FFT-based EBD algorithm is introduced, which eliminates the need for filter banks and discrete wavelet packet transform to channelize the input signal. The proposed method enables the utilization of the EBD algorithm in high-resolution spectrum sensing approaches. Moreover, it enables the detection of signals with SNRs as low as -10 dB. A low-power, area-efficient yet real-time...
A low power, eight-phase LC-ring oscillator for clock and data recovery application
, Article 2012 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, INMMIC 2012 ; 2012 ; 9781467329491 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
2012
Abstract
A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center...
Multi-level asynchronous delta-sigma modulation based ADC
, Article ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings, 12 June 2012 through 14 June 2012 ; Volume 2 , June , 2012 , Pages 725-728 ; 9781457719677 (ISBN) ; Aghdam, E. N ; Najafi, V ; Sharif University of Technology
2012
Abstract
A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology
, Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
Wiley
2012
Abstract
This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including...
A full 360° vector-sum phase shifter with very low rms phase error over a wide bandwidth
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 6 PART 1 , 2012 , Pages 1626-1634 ; 00189480 (ISSN) ; Atarodi, M ; Sharif University of Technology
2012
Abstract
An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first...
Noise canceling balun-LNA with enhanced IIP2 and IIP3 for digital TV applications
, Article IEICE Transactions on Electronics ; Volume E95-C, Issue 1 , 2012 , Pages 146-154 ; 09168524 (ISSN) ; Atarodi, M
Abstract
An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing...
A low power 1-V 10-bit 40-MS/s pipeline ADC
, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 212-215 ; 9781457718458 (ISBN) ; Sharifkhani, M ; Gholami, M ; Sharif University of Technology
2011
Abstract
A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC...
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria
, Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2011 , Pages 61-64 ; 02714310 (ISSN) ; 9781424494736 (ISBN) ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This paper introduces a Dynamic Read SRAM (DRSRAM) architecture for high-density subthreshold RAM applications. DRSRAM performs a dynamic read operation to overcome the poor stability and bitline leakage problem of 6T SRAM cell in sub-threshold region. It is shown that there is fundamental limit for wordline activation time and recovery time under a given cell mismatch and bitline leakage. To verify the proposed technique, a 64128 bit array of the 6T bit-cell is simulated in 90 nm CMOS technology. The simulation results show a 100% noise margin enhancement at subthreshold region. This design operates down to 300 mV at a 1 MHz clock rate with noise margins as large as 72 mV. This design...
A 1.93 pA/√Hz transimpedance amplifier for 2.5 Gb/s optical communications
, Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2011 , Pages 2889-2892 ; 02714310 (ISSN) ; 9781424494736 (ISBN) ; Medi, A ; Saniei, N ; Sharif University of Technology
Abstract
A state-of-the-art low-noise transimpedance amplifier (TIA) for 2.5 Gb/s family is presented using IBM 0.13-m CMOS technology. This TIA would be a part of a homodyne detector in a quantum key distribution (QKD) system. In this work a thorough design methodology based on a novel analytical noise optimization is presented. Also a unique method for eliminating the DC current of the input photodiodes (PDs) is proposed. The post-layout simulation results show bandwidth of 52 kHz to 1.9 GHz, average input referred noise of 1.93 pA/√Hz, and transimpedance gain of 80 db while dissipating 12 mW from a 1.5 V power supply, including the output buffer
Implementation of a fully integrated 30-dBm RF CMOS linear power amplifier with power combiner
, Article AEU - International Journal of Electronics and Communications ; Volume 65, Issue 6 , June , 2011 , Pages 502-509 ; 14348411 (ISSN) ; Atarodi, S. M ; Sharif University of Technology
2011
Abstract
In this paper, a fully integrated 30-dBm UHF band differential power amplifier (PA) with transformer-type combiner is designed and fabricated in a 0.18-μm CMOS technology. For the high power PA design, proposed transformer network and the number of power cells is fully analyzed and optimized to find inductors dimensions. In order to improve both the linear operating range and the power efficiency simultaneously, a parallel combination of the class AB and the class C amplifier in power cells was employed. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires
New method to synthesize the frequency bands with DLL-based frequency synthesizer
, Article 2011 International Conference on Communications and Signal Processing, ICCSP 2011, Kerala, 10 February 2011 through 12 February 2011 ; 2011 , Pages 300-304 ; 9781424497980 (ISBN) ; Gholamidoon, M ; Hashemi, M ; Sharif University of Technology
Abstract
This paper presents a new architecture for a DLL based frequency synthesizer. Occupying low area, lower power consumption and phase noise are the advantages of this novel architecture. DLLs are first ordered systems, so good stability can be obtained in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. A case in point, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit is designed based on 0.13um CMOS Technology. Also power consumption trade-offs are introduced. It was shown that 27 delay cells are sufficient to...
Sub-threshold charge recovery circuits
, Article Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 3 October 2010 through 6 October 2010, Amsterdam ; 2010 , Pages 138-144 ; 10636404 (ISSN) ; 9781424489350 (ISBN) ; Mohammadi, H. G ; Ejlali, A ; IEEE; IEEE Circuits and Systems Society; IEEE Computer Society; HiPEAC Compilation Architecture ; Sharif University of Technology
2010
Abstract
Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the abovementioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to...
A 6-Bit CMOS phase shifter for S - Band
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 58, Issue 12 PART 1 , 2010 , Pages 3519-3526 ; 00189480 (ISSN) ; Azizi, M ; Kiani, M ; Medi, A ; Atarodi, M ; Sharif University of Technology
Abstract
A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications
High power amplifier based on a transformer-type power combiner in CMOS technology
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 57, Issue 11 , November , 2010 , Pages 838-842 ; 15497747 (ISSN) ; Atarodi, M ; Luong, H. C ; Sharif University of Technology
2010
Abstract
In this brief, a transformer-type power combiner for a fully integrated high-power CMOS power amplifier (PA) is presented. The proposed power combiner is composed of a number of transformers that, unlike the ones in conventional approaches, have different sizes. This leads to higher efficiency and smaller chip area. After considering several power stage topologies, analysis and optimization of the transformer network (the power combiner) are presented. To demonstrate the advantages of the proposed architecture, a 900-MHz CMOS PA with the proposed power combiner was implemented with a 0.18-μm radio-frequency CMOS process. The amplifier achieved an efficiency value of 24% at the maximum output...
A scalable offset-cancelled current/voltage sense amplifier
, Article ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 30 May 2010 through 2 June 2010, Paris ; 2010 , Pages 3853-3856 ; 9781424453085 (ISBN) ; SharifKhani, M ; Jahinuzzaman, S. M ; Sharif University of Technology
2010
Abstract
the application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. The offset cancellation phase takes place in parallel to the wordline decoding time in order to speed up the current sensing. The proposed scheme requires a small power budget due to a self shut off mechanism. In addition to presenting a comparison with...