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electric-power-utilization
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A hierarchical sub-chromosome genetic algorithm (Hsc-ga) to optimize power consumption and data communications reliability in wireless sensor networks
, Article Wireless Personal Communications ; Volume 80, Issue 4 , 2015 , Pages 1579-1605 ; 09296212 (ISSN) ; Esmaeelzadeh, V ; Eslami, M ; Sharif University of Technology
Abstract
High reliability and low power consumption are among the major requirements in design of wireless sensor networks (WSNs). In this paper, a multi-objective problem is formulated as a Joint Power consumption and data Reliability (JPR) optimization problem. For this purpose, a connected dominating set (CDS)-based topology control approach is proposed. Our objective is to self-organize the network with minimum interference and power consumption. We consider the power changes into a topology with minimum CDS infrastructure subject to connectivity constraints. Since this problem is NP-hard, it cannot be dealt with using polynomial-time exact algorithms. Therefore, we first present a genetic...
A distributed task migration scheme for mesh-based chip-multiprocessors
, Article Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings, 20 October 2011 through 22 October 2011 ; Oct , 2011 , Pages 24-29 ; 9780769545646 (ISBN) ; Modarresi, M ; Sarbazi Azad, H ; Sharif University of Technology
Abstract
A task migration scheme for homogeneous chip multiprocessors (CMP) is presented in this paper. The proposed migration mechanism focuses on the communication sub-system and aims to reduce the total power consumption and latency of the network-on-chip (NoC). In this work, starting from an initial mapping, the tasks migrate to new cores in such a way that the distance between the end-point nodes of high-volume communication flows is reduced. Finding the new place for a task is done in a distributed manner by applying an iterative local search that relies on the local information of each task about its communication demand. The task migration procedure also includes a pre-migration step that...
3D-DPS: An efficient 3D-CAC for reliable data transfer in 3D ICs
, Article Proceedings - 2016 12th European Dependable Computing Conference, EDCC 2016, 5 September 2016 through 9 September 2016 ; 2016 , Pages 97-107 ; 9781509015825 (ISBN) ; Rohbani, N ; Miremadi, S. G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on...
On the power allocation strategies in coordinated multi-cell networks using Stackelberg game
, Article Eurasip Journal on Wireless Communications and Networking ; Volume 2016, Issue 1 , 2016 ; 16871472 (ISSN) ; Oliaiee, A ; Behroozi, H ; Khalaj, B. H ; Sharif University of Technology
Springer International Publishing
Abstract
In this paper, we study the power allocation problem in multi-cell OFDMA networks, where given the tradeoff between user satisfaction and profit of the service provider, maximizing the revenue of the service provider is also taken into account. Consequently, two Stackelberg games are proposed for allocating proper powers to central and cell-edge users. In our algorithm, assuming the fact that users agree to pay more for better QoS level, the service provider imposes optimum prices for unit-power transmitted to users as they request different levels of QoS. In addition, in order to improve system performance at cell-edge locations, users are divided into two groups based on their distance to...
MFLP: a low power encoding for on chip networks
, Article Design Automation for Embedded Systems ; Volume 20, Issue 3 , 2016 , Pages 191-210 ; 09295585 (ISSN) ; Taassori, M ; Uysal, S ; Sharif University of Technology
Springer New York LLC
2016
Abstract
Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approach assigns the symbols to data word in such a way that the more frequent words are sent by less power consumption. This algorithm dedicates the symbols with less ones to high probability data and uses transition signaling to transmit data. The proposed method, unlike the existing low power encoding, does not rely on spatial redundancy and keeps the...
A low-power high-speed comparator for analog to digital converters
, Article 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 2010-2013 ; 02714310 (ISSN); 9781479953400 (ISBN) ; Baraani Dastjerdi, M ; Fotowat Ahmadi, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power...
A novel PSO (Particle Swarm Optimization)-based approach for optimal schedule of refrigerators using experimental models
, Article Energy ; Volume 107 , 2016 , Pages 707-715 ; 03605442 (ISSN) ; Ranjbar, H ; Hatami, A ; Iman Eini, H ; Sharif University of Technology
Elsevier Ltd
2016
Abstract
Refrigerators have considerable share of residential consumption. They can be, however, flexible loads because their operating time and consumption patterns can be changed to some extent. Accordingly, they can be selected as a target for the study of Demand Side Management plans. In this paper, two experimental models for a refrigerator are derived. In obtaining the first model, following assumptions are made: the ambient temperature of refrigerator is assumed to be constant and the refrigerator door is remained closed. However, in the second model the variation of ambient temperature and door-opening effects are considered according to some general patterns. Further, two strategies are...
High-speed low-power comparator for analog to digital converters
, Article AEU - International Journal of Electronics and Communications ; Volume 70, Issue 7 , 2016 , Pages 886-894 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH
Abstract
A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing...
Reconfigurable multicast routing for Networks on Chip
, Article Microprocessors and Microsystems ; Volume 42 , 2016 , Pages 180-189 ; 01419331 (ISSN) ; Sarbazi Azad, H ; Khademzadeh, A ; Sharif University of Technology
Elsevier
Abstract
Several unicast and multicast routing protocols have been presented for MPSoCs. Multicast protocols in NoCs are used for cache coherency in distributed shared memory systems, replication, barrier synchronization, or clock synchronization. Unicast routing algorithms are not suitable for multicast, as they increase traffic, congestion and deadlock probability. Famous multicast schemes such as tree-based and path-based schemes have been proposed originally for multicomputers and recently adapted to NoCs. In this paper, we propose a switch tree-based multicast scheme, called STBA. This method supports tree construction with a minimum number of routers. Our evaluation results reveal that, for...
An operating system level data migration scheme in hybrid DRAM-NVM memory architecture
, Article Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 14 March 2016 through 18 March 2016 ; 2016 , Pages 936-941 ; 9783981537062 (ISBN) ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
With the emergence of Non-Volatile Memories (NVMs) and their shortcomings such as limited endurance and high power consumption in write requests, several studies have suggested hybrid memory architecture employing both Dynamic Random Access Memory (DRAM) and NVM in a memory system. By conducting a comprehensive experiments, we have observed that such studies lack to consider very important aspects of hybrid memories including the effect of: a) data migrations on performance, b) data migrations on power, and c) the granularity of data migration. This paper presents an efficient data migration scheme at the Operating System level in a hybrid DRAM-NVM memory architecture. In the proposed...
Thermal and power aware task mapping on 3D Network on Chip
, Article Computers and Electrical Engineering ; Volume 51 , 2016 , Pages 157-167 ; 00457906 (ISSN) ; Mehdizadeh Amiraski, A ; Hessabi, S ; Sharif University of Technology
Elsevier Ltd
Abstract
High integration and increased elements density in 3D Network on Chip (NoC) will cause more energy consumption and high temperature on chip. By mapping those tasks that have data communication between them to near cores, the communication delay and therefore, power consumption will be reduced. In addition, mapping the tasks to cores that are near the heat sink, in such a way that the generated heat is distributed indiscriminately all over the chip, will decrease maximum chip temperature. In this paper, we propose a task mapping method based on fuzzy logic that aims to alleviate power and thermal problems in 3D-NoCs. In this method, the weight of task mapping factors can be changed according...
An energy efficient target tracking scheme for distributed wireless sensor networks
, Article Proceedings of the 2009 6th International Symposium on Wireless Communication Systems, ISWCS'09, 7 September through 10 September ; 2009 , Pages 136-140 ; 9781424435845 (ISBN) ; Abolhassani, B ; Abdizadeh, M ; Sharif University of Technology
Abstract
We study the problem of power optimization for object tracking using distributed Wireless Sensor Networks (WSNs). The accuracy of the object tracking is dependent on the tracking time interval. Smaller tracking time interval increases the accuracy of tracking a moving object. However, this increases the power consumption significantly. This paper proposes a modified adaptive sleep time management scheme called Modified Predict and Mesh (MPaM) to adapt tracking time interval such that it minimizes power consumption while keeping an acceptable tracking accuracy. Also a quantitative analysis to compare the performances of the conventional PaM and proposed Modified PaM (MPaM) schemes is...
Run-time adaptive power-aware reliability management for many-cores
, Article IEEE Design and Test ; 2017 ; 21682356 (ISSN) ; Ejlali, A ; Shafique, M ; Sharif University of Technology
Abstract
Escalating reliability threats and performance issues due to process variations under the tight power envelopes of multi- /many-core chips challenge the cost-effective deployment of future technology nodes. We propose an adaptive run-time system that synergistically integrates heterogeneous hardening modes at both hardware and software levels, and selects appropriate hardening modes for concurrently executing applications under total chip power budget and timing constraints, while optimizing for reliability. To enable a high level of adaptability, we perform a comprehensive analysis of various design tradeoffs and study the impact of hardware/software hardening modes in terms of achieved...
Hierarchical stochastic models for performance, availability, and power consumption analysis of iaaS clouds
, Article IEEE Transactions on Cloud Computing ; 2017 ; 21687161 (ISSN) ; Entezari Maleki, R ; Rashidi, L ; Trivedi, K. S ; Ardagna, D ; Movaghar, A ; Sharif University of Technology
Abstract
Infrastructure as a Service (IaaS) is one of the most significant and fastest growing fields in cloud computing. To efficiently use the resources of an IaaS cloud, several important factors such as performance, availability, and power consumption need to be considered and evaluated carefully. Evaluation of these metrics is essential for cost-benefit prediction and quantification of different strategies which can be applied to cloud management. In this paper, analytical models based on Stochastic Reward Nets (SRNs) are proposed to model and evaluate an IaaS cloud system at different levels. To achieve this, an SRN is initially presented to model a group of physical machines which are...
Flexibility scheduling for large customers
, Article IEEE Transactions on Smart Grid ; 2017 ; 19493053 (ISSN) ; Parvania, M ; Fotuhi Firuzabad, M ; Rajabi Ghahnavieh, A ; Sharif University of Technology
Abstract
Large customers are considered as major flexible electricity demands which can reduce their electricity costs by choosing appropriate strategies to participate in demand response programs. However, practical methods to aid the large customers for handling the complex decision making process for participating in the programs have remained scarce. This paper proposes a novel decision-making tool for enabling large customers to determine how they adjust their electricity usage from normal consumption patterns in expectation of gaining profit in response to changes in prices and incentive payments offered by the system operators. The proposed model, formulated as a mixed-integer linear...
Performance and power modeling and evaluation of virtualized servers in IaaS clouds
, Article Information Sciences ; Volume 394-395 , 2017 , Pages 106-122 ; 00200255 (ISSN) ; Sousa, L ; Movaghar, A ; Sharif University of Technology
Elsevier Inc
2017
Abstract
In this paper, Stochastic Activity Networks (SANs) are exploited to model and evaluate the power consumption and performance of virtualized servers in cloud computing. The proposed SAN models the physical servers in three different power consumption and provisioning delay modes, switching the status of the servers according to the workload of the corresponding cluster if required. The Dynamic Voltage and Frequency Scaling (DVFS) technique is considered in the proposed model for dynamically controlling the supply voltage and clock frequency of CPUs. Thus, Virtual Machines (VMs) on top a physical server can be divided into several power consumption and processing speed groups. According to the...
An efficient numerical-based crosstalk avoidance codec design for NoCs
, Article Microprocessors and Microsystems ; Volume 50 , 2017 , Pages 127-137 ; 01419331 (ISSN) ; Mozafari, F ; Miremadi, S .G ; Sharif University of Technology
Elsevier B.V
2017
Abstract
With technology scaling, crosstalk fault has become a serious problem in reliable data transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on transition patterns appearing on the wires of NoC channels. Among these patterns, Triplet Opposite Direction (TOD) imposes the worst crosstalk effects. Crosstalk Avoidance Codes (CACs) are the overhead-efficient mechanisms to tackle TODs. The main problem of CACs is their high imposed overheads to NoC routers. To solve this problem, this paper proposes an overhead-efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits...
A high-speed method of dynamic comparators for sar analog to digital converters
, Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-Amplifier stage) is limited to V dd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above V dd=2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster...
An ultra low-power DAC with fixed output common mode voltage
, Article AEU - International Journal of Electronics and Communications ; Volume 96 , 2018 , Pages 279-293 ; 14348411 (ISSN) ; Saeidi, R ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH
2018
Abstract
A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes....
An efficient and low power one-lambda crosstalk avoidance code design for network on chips
, Article Microprocessors and Microsystems ; Volume 63 , 2018 , Pages 36-45 ; 01419331 (ISSN) ; Mahdavi, Z ; Sharif University of Technology
Abstract
Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based Crosstalk Avoidance Codes (CACs). Numeral-based CACs reduce crosstalk faults by preventing specific transition patterns to occur. One-Lambda Codes (OLCs) are the most efficient types of CACs. However, the codec of OLCs imposes overheads including power consumption, critical path and area occupation to the routers of NoCs. To find overhead-efficient OLCs, this paper proposes an Algorithm for Generating OLC Numeral systems (AGON). AGON provides a tradeoff for designers in selecting overhead-efficient OLCs. Using...