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Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance
, Article IET Circuits, Devices and Systems ; Volume 2, Issue 5 , 2008 , Pages 409-421 ; 1751858X (ISSN) ; Saffari, M ; Atarodi, M ; Tajalli, A ; Sharif University of Technology
2008
Abstract
A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps...
A CMOS implementation of simplified Linear Oscillatory Neuron (LON) model derived from FitzHugh - Nagumo model, application in artificial neural networks
, Article WSEAS Transactions on Circuits and Systems ; Volume 5, Issue 6 , 2006 , Pages 863-871 ; 11092734 (ISSN) ; Sadughi, S ; Sharif University of Technology
2006
Abstract
During this paper, a new simplified model is introduced for a neuron membrane, which is more or less, capable to mimic the dynamics of any specific physiological neuron membrane. This model is called Linear Oscillatory Neuron (LON) model, which is derived through special method of linearization applied to FitzHugh Nagumo[8] model in the neuron rest regime. As well, this linear model is terminated by a well known nonlinear system to achieve oscillatory and chaotic output, as it is observed in real neurons. Although some relatively exact models exist for special neurons, such as HH model [1,2] for giant axon of a squad (which is extracted through a Voltage clamp trial and curve fitting...
A 7 bit, 3 GHz bandwidth random-time-interleaved-hybrid DAC using a novel self-healing structure for DCE in 65 nm CMOS technology
, Article AEU - International Journal of Electronics and Communications ; Volume 134 , 2021 ; 14348411 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier GmbH
2021
Abstract
The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of...
Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors
, Article Analog Integrated Circuits and Signal Processing ; 2021 ; 09251030 (ISSN) ; Sadughi, S ; Razaghian, F ; Sharif University of Technology
Springer
2021
Abstract
A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of...
Low-voltage CMOS transconductor-C filter design using charge-pump circuit
, Article Analog Integrated Circuits and Signal Processing ; Volume 44, Issue 3 , 2005 , Pages 219-229 ; 09251030 (ISSN) ; Atarodi, M ; Sharif University of Technology
2005
Abstract
A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a...
From continuous to quantized charging response of silicon nanocrystals obtained by ultra-low energy ion implantation
, Article Solid-State Electronics ; Volume 49, Issue 7 , 2005 , Pages 1198-1205 ; 00381101 (ISSN) ; Grisolia, J ; Ben Assayag, G ; Coffin, H ; Atarodi, S. M ; Claverie, A ; Sharif University of Technology
2005
Abstract
In this paper, we present a study on the contribution of silicon nanocrystals to the electrical transport characteristics of large (100 μm × 100 μm) and small (100 nm × 100 nm) metal-oxide-semiconductor (MOS) capacitors at room temperature. A layer of silicon nanocrystals is synthesized within the oxide of these capacitors by ultra-low energy ion implantation and annealing. Several features including negative differential resistance (NDR), sharp current peaks and random telegraph signal (RTS) are demonstrated in the current-voltage and current-time characteristics of these capacitors. These features have been associated to charge storage in silicon nanocrystals and to the resulting Coulomb...
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using 'Slew boost' technique
, Article 2003 International Symposium on Low Power Electronics and Design, ISLPED 2003, 25 August 2003 through 27 August 2003 ; Volume 2003-January , 2003 , Pages 340-344 ; 15334678 (ISSN); 158113682X (ISBN) ; Mehrmanesh, S ; Vahidfar, M. B ; Safarian, A. Q ; Lotfi, R ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2003
Abstract
An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM
A novel design methodology for low-noise and high-gain transimpedance amplifiers
, Article Proceedings of the 2014 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2014 ; 2014 , pp. 77-82 ; ISBN: 9789871907861 ; Medi, A ; Bozorgzadeh, B ; Saniei, N ; Sharif University of Technology
Abstract
This paper reports on design and measurement results of a state of the art low-noise and high-gain transimpedance amplifier (TIA) implemented in 0.18 μm TSMC CMOS technology. Thorough design methodology for high gain and low power TIA design for 2.5 Gb/s optical communication circuits family is presented. A noiseless capacitive feedback is proposed and implemented as a noise efficient feedback network for TIA circuits. Besides, analytical noise calculations in this family of TIA circuits are presented and optimum noise criteria are derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes (PDs) is addressed and a circuit level...
A subthreshold symmetric SRAM cell with high read stability
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Vol. 61, issue. 1 , Jan , 2014 , p. 26-30 ; 15497747 ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition,...
A real-time, low-power implementation for high-resolution eigenvalue-based spectrum sensing
, Article Analog Integrated Circuits and Signal Processing ; Volume 77, Issue 3 , December , 2013 , Pages 437-447 ; 09251030 (ISSN) ; Shabany, M ; Sharif University of Technology
2013
Abstract
In this paper, a novel multiple antenna, high-resolution eigenvalue-based spectrum sensing algorithm based on the FFT of the received signal is introduced. The proposed platform overcomes the SNR wall problem in the conventional energy detection (ED) algorithm, enabling the detection of the weak signals at -10 dB SNR. Moreover, the utilization of FFT for the input signal channelization provides a simple, low-power design for a high-resolution spectrum sensing regime. A real-time, low-area, and low-power VLSI architecture is also developed for the algorithm, which is implemented in a 0.18 μm CMOS technology. The implemented design is the first eigenvalue-based detection (EBD) architecture...
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
, Article Integration, the VLSI Journal ; Volume 46, Issue 4 , September , 2013 , Pages 413-426 ; 01679260 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2013
Abstract
As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When...
Novel MIMO detection algorithm for high-order constellations in the complex domain
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 5 , 2013 , Pages 834-847 ; 10638210 (ISSN) ; Shabany, M ; Sharif University of Technology
2013
Abstract
A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of the search tree on demand, rather than exhaustively, as well as a new distributed sorting scheme to keep track of the best candidates at each search phase. Its support of unbounded infinite lattice decoding distinguishes the present method from previous K-Best strategies and also allows its complexity...
A low-latency low-power QR-decomposition ASIC implementation in 0.13 μm CMOS
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 2 , 2013 , Pages 327-340 ; 15498328 (ISSN) ; Patel, D ; Gulak, P. G ; Sharif University of Technology
2013
Abstract
This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip,...
A VLSI architecture for multiple antenna eigenvalue-based spectrum sensing
, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; December , 2012 , Pages 153-156 ; 9781467312615 (ISBN) ; Shabany, M ; Sharif University of Technology
2012
Abstract
An Eigenvalue-based detection (EBD) scheme, is proposed as an efficient method to overcome the noise uncertainty and the SNR wall problem in conventional energy detection (ED) schemes. Despite remarkable efforts made to analyze the EBD performance, a VLSI implementation is missing in literature. In this paper, a new FFT-based EBD algorithm is introduced, which eliminates the need for filter banks and discrete wavelet packet transform to channelize the input signal. The proposed method enables the utilization of the EBD algorithm in high-resolution spectrum sensing approaches. Moreover, it enables the detection of signals with SNRs as low as -10 dB. A low-power, area-efficient yet real-time...
A low power, eight-phase LC-ring oscillator for clock and data recovery application
, Article 2012 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, INMMIC 2012 ; 2012 ; 9781467329491 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
2012
Abstract
A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center...
Multi-level asynchronous delta-sigma modulation based ADC
, Article ICIAS 2012 - 2012 4th International Conference on Intelligent and Advanced Systems: A Conference of World Engineering, Science and Technology Congress (ESTCON) - Conference Proceedings, 12 June 2012 through 14 June 2012 ; Volume 2 , June , 2012 , Pages 725-728 ; 9781457719677 (ISBN) ; Aghdam, E. N ; Najafi, V ; Sharif University of Technology
2012
Abstract
A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous...
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
, Article Microelectronics Journal ; Volume 43, Issue 11 , November , 2012 , Pages 766-792 ; 00262692 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2012
Abstract
As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot...
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology
, Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
Wiley
2012
Abstract
This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including...
A full 360° vector-sum phase shifter with very low rms phase error over a wide bandwidth
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 6 PART 1 , 2012 , Pages 1626-1634 ; 00189480 (ISSN) ; Atarodi, M ; Sharif University of Technology
2012
Abstract
An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first...
Noise canceling balun-LNA with enhanced IIP2 and IIP3 for digital TV applications
, Article IEICE Transactions on Electronics ; Volume E95-C, Issue 1 , 2012 , Pages 146-154 ; 09168524 (ISSN) ; Atarodi, M
Abstract
An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing...