Sharif Digital Repository

A recent computational result suggests that highly confined modes can be realized by all-dielectric metamaterials. This substantially decreases crosstalk between dielectric waveguides, paving the way for high-density photonic circuits. Here, we experimentally demonstrate, on a standard silicon-on-insulator platform, that using a simple metamaterial between two silicon strip waveguides results in about a tenfold increase in coupling length. The proposed structure may lead to significant reduction in the size of devices in silicon photonics  

In this paper, we have proposed, designed, implemented, and characterized a low-cost camera-based microarray scanner which is capable of imaging fluorescently-labeled DNA or Protein microarrays. The proposed system is designed to simultaneously measure two different fluorescent dyes using two parallel channels which increase the overall scan speed. We have shown that the wide dynamic range of system makes it able to detect fluorophore densities from 100-106 molecule/μm2. In each capture, a 5.6 mm × 3.7 mm field is imaged on a 22.3 mm × 14.9 mm (18 megapixels) CMOS sensor. Therefore, the microarray can be scanned with ∼ 1μm2 spatial resolution which is high enough to distinguish borders of... 

Scaling of CMOS devices being aggressively decreasing by reduce of transistor dimensions. However, such level of integration leads to many physical limit and transistors cannot get much smaller than their current size. Quantum-dot Cellular Automate is a novel technology which significantly reduces physical limit of CMOS devices implementation, thus, it can be an appropriate candidate to be substituted for CMOS technology. In addition to high integration density of QCA circuits, other unique specifications such as high speed and low power consumption encourage researchers to utilize this technology instead of CMOS technology. In this paper, a new layout of XOR gate is presented in QCA... 

Radiation-induced multiple event transients (METs) are expected to become more frequent than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a fast and accurate layout-based soft error rate (SER) assessment technique with consideration of both SET and MET fault models is presented. Despite existing techniques in which the adjacent MET sites are extracted from a logic-level netlist, we conduct a comprehensive layout analysis to obtain MET adjacent cells. Experimental results reveal that the layout-based technique is the only viable solution for identification of the adjacent cells as netlist-based techniques considerably underestimate the overall SER.... 

This paper presents the theoretical introduction and experimental validation of the "Class-J2 Mode Power Amplifier," which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J2 PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to... 

A low-power wide-range CMOS temperature sensor architecture is proposed for RFID and Sensor Networks based on temperature-to-frequency conversion using supply voltage controlled sub-threshold ring oscillator. The principles of operation are investigated and proved via simulation results. Most errors are canceled out by this ratio-metric design. An inaccuracy of -0.84°C to +0.34°C occurs over a range of -40°C to 80°C after using a novel in-field digital two-point calibration. The entire sensor consumes less than 93nW to 305nW over the temperature range and can be digitally reconfigured for setting sample rate and resolution in a tradeoff. © 2016 IEEE  

In this brief, modifications to the peaking current reference with MOS transistors operating in the subthreshold and the strong inversion region has been proposed by means of which very small currents with immunity to temperature variations on a chip can be obtained. Temperature compensation can be done by adding a source degeneration resistor to the conventional peaking current source structure. Design examples are provided for both weak and strong inversion operations with output currents of 1.5 μA and 40 μ A with less than 4% and 10% variation over the span of-40 °C to +100 °C, respectively. A prototype of the circuit operating in the weak and strong inversion region is designed,... 

In this paper, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the... 

In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively  

In this brief, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the... 

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB... 

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125-and 3.9-ps delay resolution, designed and fabricated in a 0.18-μ m CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2-23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8-18... 

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125-and 3.9-ps delay resolution, designed and fabricated in a 0.18-μ m CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2-23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8-18... 

A high-precision delay chain circuit integrated in a 0.18- mu ext{m} CMOS technology working in the frequency bandwidth of 8-18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay... 

Design of a novel RF front - end structure for 2450-MHz Band IEEE 802.15.4 ZigBee standard in a 0.18-μm CMOS process is presented. Utilizing a common-gate structure instead of conventional inductive degenerated common source amplifier, Low noise figure is achieved with LNA bias current as low as 1mA. An analytical method is presented to minimize the Noise figure of proposed common-gate LNA structure. Together with the LNA, an active Gilbert Cell mixer is adopted to convert the RF signal to 2MHz IF signal. Employing an enhanced current re-use structure, simulation results show a conversion gain of 37.7dB, a Noise figure of 5.9dB and an IIP3 of -4dBm for the front -end. The RF front - end... 

A 1.8V, 10-Bit, 40-MS/s Pipeline analog-to-digital converter designed using 0.18-μmCMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free- dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5mW.... 

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and... 

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM  

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with 0.18μ m CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the... 

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and...