Sharif Digital Repository

A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two subblocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full... 

This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU).... 

In this work, we study the conductance of a general periodic quantum dot (QD) attached to ideal semi-infinite uniform metallic leads (nanocrystals), fully analytically. We propose a new general formula which relates conductance to transfer matrix (TM) for an isolated cell in the periodic dot. The equation describes exactly the dependence of the transmission coefficient (TC) on Fermi energy, dot-size, dot-lead coupling, and gate voltage for an arbitrary periodic dot. Then, we derive a nonlinear equation which gives the resonance, bound, and surface state energies. Finally, the TC has been calculated for gapless, single, and double gap models exactly. Moreover, we have also calculated the... 

Anodic aluminum oxide (AAO) was used as a template to prepare highly ordered Ni-Fe-Co alloy nanowire arrays. This membrane was fabricated with two-step anodizing method. It is found that there is an optimum barrier thickness to obtain a successful electrodeposition in pores of AAO. The thickness of barrier layer can be modified by additional electrochemical process after completing the anodizing step. Barrier layer thinning can create a rooted structure at the bottom side of the AAO pores and the electrodeposited nanowire arrays. The triple Ni-Fe-Co alloy was deposited in AAO membrane by ac voltage in a simple sulfate bath. The composition of nanowires shows anomalous deposition features... 

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a... 

Power transformer monitoring as a reliable tool for maintaining purposes of this valuable asset of power systems has always comprised partial discharge offline measurements and online monitoring. The reason lies in non-destructive feature of PD monitoring. Partial discharge monitoring helps to detect incipient insulation faults and prevent insulation failure of power transformers. This paper introduces a software package developed based on structural data of power transformer and discusses the results of the simulation on Abetti winding, which might be considered as a basic layer winding. A hybrid model is used to model the transformer winding, which has been developed by first author.... 

A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51mW/Channel/Gbps while occupies 0.045mm2 silicon area. Copyright 2005 ACM  

The temperature and voltage dependence of spin transport is theoretically investigated in a new type of magnetic tunnel junction, which consists of two ferromagnetic outer electrodes separated by a ferromagnetic barrier and a nonmagnetic (NM) metallic spacer. The effect of spin fluctuation in magnetic barrier, which plays an important role at finite temperature, is included by taking the mean-field approximation. It is found that, the tunnel magnetoresistance (TMR) and the electron-spin polarization depend strongly on the temperature and the applied voltage. The TMR and spin polarization at different temperatures show an oscillatory behavior as a function of the NM spacer thickness. Also,... 

The spin-polarized transport is investigated in a new type of magnetic tunnel junction which consists of two ferromagnetic electrodes separated by a magnetic barrier and a nonmagnetic metallic spacer. Based on the transfer matrix method and the nearly-free-electron approximation the dependence of the tunnel magnetoresistance (TMR) and electron-spin polarization on the nonmagnetic layer thickness and the applied bias voltage are studied theoretically. The TMR and spin polarization show an oscillatory behaviour as a function of the spacer thickness and the bias voltage. The oscillations originate from the quantum well states in the spacer, while the existence of the magnetic barrier gives rise... 

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS oscillator is presented. A simplified model to predict the phase noise performance for this type of oscillator is developed. Using this method, it becomes possible to design an optimised oscillator in terms of a minimum phase noise and low power consumption. The validity of the method has been verified by designing a LC CMOS oscillator using 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of the supply voltage  

An analytic method for prediction of oscillation amplitude and supply current of differential CMOS oscillators is presented. The validity of this method has been verified by designing an LC CMOS oscillator in a 0.24 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage  

The slow kinetics of wettability alteration toward a more water-wetting state by low-salinity waterflooding (LSWF) in oil-brine-rock (OBR) systems is conjectured to be pertinent to the electrokinetic phenomena in the thin brine film. We hypothesize that the nanoscale physicochemical heterogeneities such as surface roughness and surface charge heterogeneity at the rock/brine interface control further the dynamics of electrodiffusion and electrostatic disjoining pressure (Πel), thus the time-scale and the magnitude of the low salinity effect (LSE). In this regard, film-scale computational fluid dynamics (CFD) simulations were performed. The coupled Poisson-Nernst-Planck (PNP) equations were...