Sharif Digital Repository

Multi-turn resolvers are proposed to be used in high accuracy, high-reliability applications that need to have the benefits of absolute measurement and high accuracy, simultaneously. In this paper, the influence of different arrangements of rotary transformer (RT) and resolvers' core on the accuracy of a multi-turn wound rotor (WR) resolver is discussed. Then, an optimal configuration with the aim of reducing the total cost, and the total volume of the sensor is proposed. All the analysis is done using 3-D time-variant finite element method (3-D TVFEM) and the optimal structure is built for experimental tests. Finally, experimental measurements are employed to verify the simulation results.... 

A novel machine learning (ML) clustering algorithm, named light-fidelity (LiFi) Grid, is proposed to design amorphous cells of LiFi access points (APs) in order to maximize the minimum signal-to-interference-plus-noise ratio (SINR) from the viewpoint of user-centric (UC) network design. The algorithm consists of two phases. Explicitly, the first phase consists of finding clusters of user densities based on the mean-shift (MS) clustering algorithm. In contrast to some other clustering algorithms, such as K-means, MS does not need to know the number of clusters in advance. Furthermore, the combined transmission scheme is assumed in each cell. In the second phase, this paper proposes a novel... 

Purpose: This paper aims to propose a novel matrix-based systematic approach for vulnerability assessment. Design/methodology/approach: The proposed method consists of two major steps. First, the power network is modeled as a topological combination of edges (transmission lines, transformers, etc.) and nodes (buses, substations, etc.). The second step is to use an axiomatic design-based index for topology analysis. This index is based on the systematic counting of possible routes from the start (generators) to destination (loads), considering load importance, before and after a disruption. Findings: The effectiveness of the proposed method is demonstrated through an illustrative example and... 

This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The...