Sharif Digital Repository

This paper presents an efficient High-Level Synthesis (HLS) approach to improve RT-Level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-Level controller to locate the faults. The fault detection step is based on a genetic algorithm (GA) search technique. This genetic algorithm is applied to the design after high level synthesis process to explore the test map. The proposed method has been evaluated based on dependability enhancement and area/latency overhead imposed to different benchmarks after... 

Since the failure of resources fatally affects processor allocation, a fault tolerant service is essential in the interconnection networks. In this paper, a new fault tolerant method is proposed and evaluated in the hybrid processor allocation scheme, which we have introduced in our previous work. Our task consists of two independent phases. First, the allocation process executes to allocate an efficient set of processors to the requested submesh. The second phase comes to work when the faulty nodes are detected in the allocated spaces. The selected processor allocation scheme allows jobs to be executed without waiting, provided that the number of processors is sufficient in the system and... 

Purpose: The purpose of this paper is to identify the fault modes of a nonlinear twin-rotor system (TRS) using the subspace technique to facilitate fault identification, diagnosis and control applications. Design/methodology/approach: For identification of fault modes, three types of system malfunctions are introduced. First malfunction resembles actuator, second internal system dynamics and third represents sensor malfunction or offset. For each fault scenario, the resulting TRS model is applied with persistently exciting inputs and corresponding outputs are recorded. The collected input–output data are invoked in NS4SID subspace system identification algorithm to obtain the unknown fault... 

This paper presents a fault tolerant routing algorithm for the star graph. The algorithm is based on the concept of unsafely vectors originally proposed for binary n-cubes. Each node starts by computing a first level unsafety set,composed of the set of unreachable neighbours.It then performs some exchanges with its neighbours to determine the unsafety nodes.After that all of the nodes have the addresses of all faulty nodes. Based on the information gathered in each nodefault-tolearnt routing between a source node and a destination node is raelised  

Information integrity in cache memories is a fundamental requirement for dependable computing. As caches comprise much of a CPU chip area and transistor counts, they are reasonable targets for single and multiple transient faults. This paper presents: 1) a fault detection scheme for tag arrays of cache memories and 2) an architectural cache to improve dependability as well as performance. In this architecture, cache space is divided into sets of different sizes and different tag lengths. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. The results show that error detection... 

This paper presents a fault injection tool, called SINJECT that supports several synthesizable and non-synthesizable fault models for dependability analysis of digital systems modeled by popular HDLs. The tool provides injection of transient and permanent faults into the Verilog as well as VHDL models of a digital circuit to study the fault behavior, fault propagation and fault coverage. Moreover, using specific simulators, the SINJECT provides a mixed-mode fault injection, i.e., fault injection into both Verilog and VHDL parts of a model, to achieve high description reality by Verilog and high capability modeling by VHDL. To demonstrate the tool, two case studies are evaluated: 1) an... 

Fast fault detection and converter reconfiguration is necessary for fault tolerant doubly fed induction generator (DFIG) in wind energy conversion systems (WECS) to prevent further damage and to make possible the continuity of service. Extra sensors are needed in order to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A fault tolerant converter topology for this application is studied. Control and fault detection system are implemented on a single FPGA and Hardware in the Loop experiments are performed to evaluate the proposed detection scheme, the digital controller and the fault... 

Let P be a set of points in the plane, each equipped with a directional antenna that can cover a sector of angle α and range r. In the symmetric model of communication, two antennas u and v can communicate to each other, if and only if v lies in u’s coverage area and vice versa. In this paper, we introduce the concept of fault-tolerant spanners for directional antennas, which enables us to construct communication networks that retain their connectivity and spanning ratio even if a subset of antennas are removed from the network. We show how to orient the antennas with angle α and range r to obtain a k-fault-tolerant spanner for any positive integer k. For α ≥ π, we show that the range 13 for... 

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer... 

Network survivability refers to the ability of a network to maintain uninterrupted service regardless of the scale, magnitude, duration, and the type of failures. There is growing interest in attempts to quantify the network survivability in presence of various failures. We perceive that both performance and availability are integral components of survivability. Therefore, we propose a general composite model for survivability performance evaluation which is applicable to a wide range of networks. In this model, the excess loss due to failure (ELF) analysis is used to find the loss due to failure when the system is operating in gracefully degraded states. Fault tree method is used to model... 

A short circuit fault in an AC railway supply system could have undesired consequences; including high-amplitude current flow in the power path, the rail potential rise in the fault vicinity. This paper studies the problem of the rail voltage rise in Tehran-Karaj railway system by the use of a steady state circuit model for the AC autotransformer during a phase-to-ground fault. By using this model, all the currents and voltages of the system can be easily calculated for all possible short circuit fault locations. With the help of the derived analytical model, one can also predict the possible fault locations which may cause the protection system to operate. The estimation of the system... 

In this paper, an FPGA-controlled fault tolerant back-to-back converter for DFIG-based wind energy conversion application is studied. Before an open-circuit failure in one of the semiconductors, the fault tolerant converter operates as a conventional back-to-back six-leg one. After the fault occurrence in one of the switches, the converter will continue its operation with the remaining five healthy legs. Design, implementation, simulation and experimental verification of a reconfigurable control strategy for the fault tolerant six/five leg converter used in wind energy conversion are discussed. The proposed reconfigurable control strategy allows the uninterrupted operation of the converter... 

In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably... 

Medium power distributed energy resources (DERs) are commonly connected to medium voltage distribution systems via voltage source converters (VSCs). Several guidelines and standards have been developed to establish the needed criteria and requirements for DERs interconnections. In this respect, it is preferred to reinforce the VSC fault ride through (FRT) capability, which considerably minimizes the DG outage period and reconnection time and results in a resilient system against short circuits. Considering the significant number of asymmetrical faults in distribution systems, the VSC response in such conditions must be investigated, and consequently, its FRT capability must be reinforced. In... 

Winding turn-to-turn fault (TTF) is one of the most reported reasons for transformer unplanned outage. If its occurrence is not detected at an early stage, it can develop into a costly phase-to-ground fault. In this paper, a novel algorithm based on the fault-related incremental currents is proposed to detect a low-level transformer TTF. This paper shows that the performance of the proposed method is independent of the transformer operating condition. Therefore, it is reliable even under the presence of power system transients such as the external faults. In addition, the proposed algorithm can be configured uniquely and easily. This feature prevents the algorithm from unnecessary trips.... 

This study presents a novel method for fault location of transmission lines by multiple fault current measurements. In contrast to conventional methods, it is proposed to utilise several current measurements, which may be far from the faulted line. The circuit equations of the network are used to express each fault current as a function of fault location. Fault location is then estimated using a least-squares estimation technique. To achieve a robust estimation of fault location, statistical hypotheses-testing is employed for identifying erroneous measurements. The method is applicable to both synchronised and unsynchronised measurements. Moreover, fault location can be estimated regardless... 

Fast fault detection and reconfiguration is necessary in power electronic converters in lots of applications to prevent further damage and to make possible the continuity of service. In this paper a very fast fault detection scheme is presented that minimizes the use of voltage sensors. A fault tolerant topology is studied. Control and fault detection system are implemented on a single FPGA and hardware in the loop experiments are performed to evaluate the detection scheme, the digital controller and the structure  

While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is...