Search for: fault-injection
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    Evaluation of babbling idiot failures in FlexRay-based networkes

    , Article IFAC Proceedings Volumes (IFAC-PapersOnline) ; Volume 7, Issue PART 1 , 2007 , Pages 399-406 ; 14746670 (ISSN); 9783902661340 (ISBN) Lari, V ; Dehbashi, M ; Miremadi, S. G ; Amiri, M ; Sharif University of Technology
    IFAC Secretariat  2007
    This paper evaluates the error propagation and its effects in babbling idiot failure in a FlexRay-based network. The evaluation is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of four nodes. Nodes in this experiment are considered in two forms: 1) node without bus guardian, 2) node with bus guardian. The results of fault injection show that in first form about 4.57% of faults lead to the babbling idiot failures. Also in second form about 0.75% faults lead... 

    A software-based concurrent error detection technique for powerPC processor-based embedded systems

    , Article 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2005, Monterey, CA, 3 October 2005 through 5 October 2005 ; 2005 , Pages 266-274 ; 15505774 (ISSN) Fazeli, M ; Farivar, R ; Miremadi, S. G ; Aitken R ; Ito H ; Metra C ; Park N ; Sharif University of Technology
    This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI).... 

    Evaluation of Fault Tolerance for SRAM-Based FPGAs by Fault Injection into Configuration Bits

    , M.Sc. Thesis Sharif University of Technology Abolhassani Ghazaani, Elyas (Author) ; Miremadi, Ghasem (Supervisor)
    Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of... 

    A fast, flexible, and easy-to-develop FPGA-based fault injection technique

    , Article Microelectronics Reliability ; Volume 54, Issue 5 , May , 2014 , Pages 1000-1008 ; ISSN: 00262714 Ebrahimi, M ; Mohammadi, A ; Ejlali, A ; Miremadi, S. G ; Sharif University of Technology
    By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities... 

    A low cost circuit level fault detection technique to full adder design

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) Mozafari, S. H ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition  

    ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 289-292 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Ebrahimi, M ; Miremadi, S. G ; Asadi, H ; Sharif University of Technology
    We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and... 

    A fast analytical approach to multi-cycle soft error rate estimation of sequential circuits

    , Article Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, 1 September 2010 through 3 September 2010, Lille ; 2010 , Pages 797-800 ; 9780769541716 (ISBN) Fazeli, M ; Miremadi, S. G ; Asadi, H ; Baradaran Tahoori, M ; Sharif University of Technology
    In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault injection approach with 92% accuracy. This makes the proposed approach applicable to industrial-scale circuits  

    Soft error modeling and remediation techniques in ASIC designs

    , Article Microelectronics Journal ; Volume 41, Issue 8 , August , 2010 , Pages 506-522 ; 00262692 (ISSN) Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain... 

    A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design

    , Article Proceedings of the International Conference on Dependable Systems and Networks, 28 June 2010 through 1 July 2010 ; June , 2010 , Pages 131-140 ; 9781424475018 (ISBN) Fazeli, M ; Miremadi, S. G ; Asadi, H ; Nematollah Ahmadian, S ; Sharif University of Technology
    In this paper, we propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates,flip-flops, and paths of a circuit. Using such information, designers can selectively protect the vulnerable parts resulting in lower power and area overheads that are the most important factors in embedded systems. Unlike previous approaches, the proposed approach firstly does not rely on fault injection or fault simulation; secondly it measures the SER for multi cycles of circuit operation; thirdly, the proposed approach accurately computes all three masking factors, namely, logical, electrical, and timing masking; fourthly, the effects of error... 

    RI-COTS: trading performance for reliability improvements in commercial of the shelf systems

    , Article 19th International Symposium on Computer Architecture and Digital Systems, CADS 2017, 21 December 2017 through 22 December 2017 ; Volume 2018-January , March , 2018 , Pages 1-6 ; 9781538643792 (ISBN) Ghasemi, G ; Hosseini Monazzah, A. M ; Farbeh, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    The flexibility of software-based fault tolerant approaches in providing the required level of reliability Commer-cial-Off-The Shelf (COTS) devices made them the first choice in designing safety-critical systems. In this paper, we propose a reliability improvement method for COTS-based systems, so-called, RI-COTS. The main idea behind RI-COTS is to establish a tradeoff between reliability and performance of COTS system through controlling redundant execution at instruction level. RI-COTS is implemented on LEON2 processor VHDL model. Our simulation results show that comparing with the most related studies, RI-COTS can improve the fault detection capability by 20% with only 4% performance... 

    A low-cost on-line monitoring mechanism for the flexray communication protocol

    , Article Proceedings - 2009 4th Latin-American Symposium on Dependable Computing, LADC 2009, 1 September 2009 through 4 September 2009, Joao Pessoa ; 2009 , Pages 111-118 ; 9780769537603 (ISBN) Sedaghat, Y ; Miremadi, G ; Sharif University of Technology
    Nowadays, communication protocols are used in safety-critical automotive applications. In these applications, fault tolerance is a main requirement and the existence of single points of failure is a serious threat to system failures. Among the communication protocols, FlexRay is expected to become the communication backbone for future automotive systems. In this paper, we identify single points of failure in the FlexRay protocol by injecting a total of 135,600 single-bit transient faults into all accessible registers of the FlexRay communication controller. The results showed that about 1.2% of all injected faults caused the controller to freeze immediately. Based on these results and... 

    A comprehensive analysis on the resilience of adiabatic logic families against transient faults

    , Article Integration ; Volume 72 , May , 2020 , Pages 183-193 Narimani, R ; Safaei, B ; Ejlali, A ; Sharif University of Technology
    Elsevier B.V  2020
    With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of... 

    Assessment of message missing failures in FlexRay-based networks

    , Article 13th Pacific Rim International Symposium on Dependable Computing, PRDC 2007, Melbourne, VIC, 17 December 2007 through 19 December 2007 ; 2007 , Pages 191-194 ; 0769530540 (ISBN); 9780769530543 (ISBN) Lari, V ; Dehbashi, M ; Miremadi, S. G ; Farazmand, N ; Sharif University of Technology
    This paper assesses message missing failures in a FlexRay-based network. The assessment is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller; the parts are: controller host interface, protocol operation control, coding and decoding unit, media access control and clock synchronization process. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. This HDL model of the controller is exploited to setup a FlexRay-based network composed of four nodes. The results of fault injection show that about 35% of faults led to the message missing failures. The controller host interface and the clock... 

    Efficient algorithms to accurately compute derating factors of digital circuits

    , Article Microelectronics Reliability ; Volume 52, Issue 6 , June , 2012 , Pages 1215-1226 ; 00262714 (ISSN) Asadi, H ; Tahoori, M. B ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single... 

    Low cost concurrent error detection for on-chip memory based embedded processors

    , Article Proceedings - 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, 24 October 2011 through 26 October 2011 ; October , 2011 , Pages 114-119 ; 9780769545523 (ISBN) Khosravi, F ; Farbeh, H ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
    This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than... 

    A multi-bit error tolerant register file for a high reliable embedded processor

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 22011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 532-537 ; 9781457718458 (ISBN) Esmaeeli, S ; Hosseini, M ; Vahdat, B. V ; Rashidian, B ; Sharif University of Technology
    The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the... 

    System-level vulnerability estimation for data caches

    , Article 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, 13 December 2010 through 15 December 2010 ; 2010 , Pages 157-164 ; 9780769542898 (ISBN) Haghdoost, A ; Asadi, H ; Baniasadi, A ; Sharif University of Technology
    Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In... 

    Feature specific control flow checking in COTS-based embedded systems

    , Article Proceedings - 3rd International Conference on Dependability, DEPEND 2010, 18 July 2010 through 25 July 2010 ; July , 2010 , Pages 58-63 ; 9780769540900 (ISBN) Rajabzadeh, A ; Miremadi, S.G ; IARIA ; Sharif University of Technology
    While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

    Classification of activated faults in the flexray-based networks

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 26, Issue 5 , October , 2010 , Pages 535-547 ; 09238174 (ISSN) Sedaghat, Y ; Miremadi, S. G ; Sharif University of Technology
    FlexRay communication protocol is expected to become the de-facto standard for distributed safety-critical systems. This paper classifies the effects of transient single bit-flip fault injections into the FlexRay communication controller. In this protocol, when an injected fault is activated, this may result in one or more error types, i.e.: Boundary violation, Conflict, Content, Freeze, Synchronization, Syntax, and Invalid frame. To study the activated faults, a FlexRay bus network, composed of four nodes, was modeled by Verilog HDL; and a total of 135,600 transient faults was injected in only one node, called the target node. The results show that only 9,342 of the faults (about 6.9%) were... 

    Complement routing: A methodology to design reliable routing algorithm for network on chips

    , Article Microprocessors and Microsystems ; Volume 34, Issue 6 , 2010 , Pages 163-173 ; 01419331 (ISSN) Patooghy, A ; Miremadi, S. G ; Sharif University of Technology
    Use of deep sub-micron VLSI technologies in fabrication of Network on Chips (NoCs) makes the reliability to be one of the first order concerns in the design of these products. This paper proposes and evaluates a methodology that adds reliability to NoC routing algorithms with minimal power and performance overheads. The key idea behind this methodology is to use the concept of complement routing in which two routing algorithms with disjoint sets of allowed turns are incorporated. According to this methodology, while a packet is routed by a routing algorithm, a redundant copy of that packet is routed by the complement of that routing algorithm. This is done by exploiting channels with lower...