Search for: fault-injection
Total 45 records
Article Proceedings of the 14th IEEE European Test Symposium, ETS 2009, 25 May 2009 through 29 May 2009, Sevilla ; 2009 , Pages 121-126 ; 9780769537030 (ISBN) ; Miremadi, G ; Sharif University of Technology
FlexRay communication protocol is expected becoming the de-facto standard for distributed safetycritical systems. In this paper, transient single bit-flip faults were injected into the FlexRay communication controller to categorize and analyze the activatedfaults. In this protocol, an activated fault results in one or more error types which are Boundary violation, Conflict, Content, Freeze, Synchronization, and Syntax. To study the activated faults, a FlexRay bus network, composed of four nodes, was modeled by Verilog HDL; and a total of 135,600 transient faults were injected in only one node, where 9,342 (6.9%) of the faults were activated. The results show that the Synchronization error is...
Article 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, Chengdu, 28 April 2009 through 29 April 2009 ; 2009 ; 9781424425877 (ISBN) ; Amiri, M. A ; Ejlali, A ; Sharif University of Technology
In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably...
Article IEEE Transactions on Reliability ; Volume 68, Issue 1 , 2019 , Pages 201-215 ; 00189529 (ISSN) ; Tahoori, M ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2019
In recent years, high availability and reliability of data storage systems (DSS) have been significantly threatened by soft errors occurring in storage controllers. Due to their specific functionality and hardware-software stack, error propagation and manifestation in DSS is quite different from general-purpose computing architectures. To the best of our knowledge, no previous study has examined the system-level effects of soft errors on the availability and reliability of DSS. In this paper, we first analyze the effects of soft errors occurring in the server processors of storage controllers on the entire storage system dependability. To this end, we implement the major functions of a...
Article 2006 International Conference on Microelectronics, ICM 2006, Dhahran, 16 December 2006 through 19 December 2006 ; 2006 , Pages 67-70 ; 1424407656 (ISBN); 9781424407651 (ISBN) ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental...
Article Industrial Embedded Systems - IES'2006, Antibes Juan-Les-Pins, 18 October 2006 through 20 October 2006 ; 2006 ; 142440777X (ISBN); 9781424407774 (ISBN) ; Fazeli, M ; Miremadi, S. G ; Sharif University of Technology
In this paper, a hardware control flow checking technique is presented and evaluated. This technique uses reconfigurable of the shelf FPGA in order to concurrently check the execution flow of the target micro processor. The technique assigns signatures to the main program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. The main characteristic of this technique is its ability to be applied to any kind of processor architecture and platforms. The low imposed hardware and performance overhead by this technique makes it suitable for those applications in which cost is a major concern, such as...