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field-programmable-gate-array--fpga
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Design and Implementation of FPGA Based Real Time Simulator for Power Electronic Converters
, M.Sc. Thesis Sharif University of Technology ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
Real-time Simulator plays an important role in the test of power electronic converters. Using of this simulators and Hardware-in-the-loop tests, cost and time of experiments will redused, furthermore those experiments which are not operative on the real system, can be achived. However, the accuracy of the used model in simulation as well as fast and easy programming of these simulators is very important. Therefore in this thesis, design and implementation of real-time simulator for power electronic converters have been discussed that in addition to high accuracy of the simulation, implementation of the several tests will be easy. As regards the power electronic switch is the most important...
A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration
, M.Sc. Thesis Sharif University of Technology ; Bayat-Sarmadi, Siavash (Supervisor)
Abstract
Hardware Trojans have emerged as a major concern for integrated circuits in recent years. As a result, detecting Trojans has become an important issue in critical applications, such as finance and health. In this work, a trusted platform for detecting Trojans in FPGA bitstreams is presented. The proposed methodology takes advantage of increased Trojan activation, caused by transition aware partitioning of the circuit, while it benefits partial reconfiguration feature of FPGAs to reduce area overhead. Simulation results, performed for the transition probability thresholds of 〖10〗^(-4) and 〖2×10〗^(-5), show that this method increases the ratio of the number of transitions in the Trojan...
RF Signal Sampling using Compress Sensing and its Implementation on FPGA
, M.Sc. Thesis Sharif University of Technology ; Pezeshk, Amir Mansour (Supervisor)
Abstract
Analog-to-digital conversion and signal processing has been increasing due to its many advantages. So that mostly we prefer to convert signal from analog area to digital samples, then they are processed and finaly put the result signal at the system output. How ever because the restriction of the sampling rate, Prevent the spread of digital processing for the high-frequency signal (RF). In recent years, ADCs sampling rate rise up to several GHz (for example ADC with 4 GSPS and 12 bits for TI) that output of the these ADCs by powerful and fast FPGAs are processed but According to Shannon theorem band width of these ADCs is not desirable.the goal of this thesis uses of the compressed sensing...
Design of a Fault Tolerant SPARC Based Micro Processor On FPGA
, M.Sc. Thesis Sharif University of Technology ; Rashidian, Bijan (Supervisor) ; Vosoughi Vahdat, Bijan (Supervisor)
Abstract
In this thesis, LEON Processor was chosen for its compatible architecture that can be implemented on a wide range of FPGAs. The final designed processor is aimed to conquer soft and hard errors that occur due to cosmic radiations in SRAM cells of an FPGA. The system can finally resist all single SEUs that happen in flip flops and all 4 random errors that take place in each register of the register file. All the flip flops and latches are protected using a TMR scheme. The information redundancy in the regiester file to overcome all 4 random errors is 168% and the errors are corrected by means of a mechanesim that is masked from the processor core. In cache memory, each 32 bit data is...
Increasing BIOS Trust in Personal Computers Using Reconfigurable Devices
, M.Sc. Thesis Sharif University of Technology ; Bayat Sarmadi, Siavash (Supervisor)
Abstract
Due to the expansion of digital system threats, trusted computation with a new approach for countering such threats has emerged. This approach is based on using a hardware module for implementing a trusted platform (TPM). TPM includes a chipset and the trusted systems core. Nowadays many of mobile computers do include this technology. This hardware creates trust using a trust chain and expanding this trust to other parts of the system. The starting point in this chain is the computer BIOS. BIOS is the first code that the system usually executes. One of the most powerful recent attacks on computer systems is to infect the BIOS and other firmware. One of such complicated attacks is the rootkit...
Evaluation of Fault Tolerance for SRAM-Based FPGAs by Fault Injection into Configuration Bits
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghasem (Supervisor)
Abstract
Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of...
A Dependable Routing Architecture for Reconfigurable Devices
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
Reconfigurable devices are a popular platform for fast prototyping of digital system due to having high performance of hardware implementation along with flexibility of software. However, reconfigurable devices suffer from area, performance and dependability gaps in comparison with their Application Specific Integrated Circuit (ASIC) counterparts, which greatly limits their application.
The dependability gap originates from the sensitivty of configuration memory to soft errors. When a reconfigurable device configuration memory is affected by soft errors, their configuration will be invalid until reconfigured. Since the routing fabric is the origion of over 80% of soft errors in...
The dependability gap originates from the sensitivty of configuration memory to soft errors. When a reconfigurable device configuration memory is affected by soft errors, their configuration will be invalid until reconfigured. Since the routing fabric is the origion of over 80% of soft errors in...
Accelerating Big Data Stream Processing by FPGA-implementation of Parts of the Topology Graph
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
In recent years, big data processing plays an important role in the era of information technology. The exponential growth of big data volume increases the need for data centers and infrastructures with more processing power. Due to dark silicon and scalability limitations in deep-submicron, the increasing trend of server performance slows down. Therefore, hardware accelerators such as FPGA and GPU are become increasingly popular for improvement of data center processing power. There are two types of big data processing based on the application: stream processing and batch processing. With the widespread use of social networks, online control systems and internet of things services, the...
Design of Fault Tolerant Processor for Implementation on SRAM Based FPGAs
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghasem (Supervisor)
Abstract
Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the...
Automatic Intra Pulse Modulation Recognition of RF Signal with FPGA Implementation
, M.Sc. Thesis Sharif University of Technology ; Pezeshk, Amir Mansour (Supervisor)
Abstract
Automatic modulation recognition is an improving area in signal processing that has been interest of research institutes in recent years. Every signal intelligence system consists of three parts: Front, middle prcessing, Output. which Automatic recognition system is in the middle processing. Vast researches has been done on front and output section. By the way output section demands proper work by modulation recognition section in order to work appropriately. With the right knowledge of the receiving modulation, output section can jam or demodulate the receiving signal by demand. Intrapulse modulation in this research is the meaningful variation of frequency, amplitude or phase of a signal....
Design and Efficient Hardware Implementation of Spiking Neural Networks on FPGA
, M.Sc. Thesis Sharif University of Technology ; Hashemi, Matin (Supervisor)
Abstract
Spiking Neural Networks(SNN) are networks which are consisted of layers of neurons, like other typical artificial neural networks. The main difference between SNN and other neural networks is the type of data transportation among neurons which is done by spikes. Spiking neural networks and their models are considered as the nearest networks and neurons to animals’ nervous systems. In aspects of hardware implementation, the type of data transportation in SNN causes them to be ultra-low power. So, implementation of these networks on chips like FPGA and also usage of SNN in applications with high processing load have startling germination, recently. In this work, we have tried to propose some...
Embedded Camera Design for Machine Vision Traffic Aplication
, M.Sc. Thesis Sharif University of Technology ; Gholampour, Iman (Supervisor)
Abstract
With the advent of technology, small in size sensors, memory, speeding up the processor and lowering the cost, it is possible to build an embedded camera system. The goal of this project is to design and build an embedded camera system so it can execute any set of necessary algorithms as depending on the application. In this project, two models of embedded camera systems have been presented as an integrated system and a system with independent units. To design the integrated embedded system, ZYNQ processor is used and two structures are presented in the form of hardware-software and hardware design. In hardware-software design, image processing operations are done by software and in hardware...
Design and Implementation of an Audio Steganography System on FPGA
, M.Sc. Thesis Sharif University of Technology ; Tabandeh, Mahmood (Supervisor)
Abstract
In recent years, along with development of technology and decrease in size of digital devices, copying and editing of digital multimedia products has become easier. Also, broadband technology caused simpler distribution of data. Considering above mentioned problems, we can use watermarking. Nowadays, watermarking has many applications such as secure transmission of data, owner identification, proof of ownership, authentication, broadcast monitoring etc. Watermarking is the process of hiding information in a secure host, in a way that it does not change the quality of signal. Watermarking is the science and art of hiding secret information in which neither the sender nor the receiver would...
A Reconfigurable Architecture Using Non-voltatile Memories
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
In recent years, emerging Non-Volatile Memories (NVMs) have become promising alternatives for existing memory technologies. Due to shortcomings of SRAM memory in nanometer era,NVMs such as Phase-Change Memory (PCM) can be used in configuration memories of Field-Programmable Gate Arrays (FPGAs). Despite prominent features of emerging NVMs, they suffer from high write-power, high write-latency, and limited number of reliable write opera-tions. In addition, a dedicated Peripheral Circuit (PC) which is required to convert the NVM state to the equivalent voltage level can impose significant area and power overheads to FPGAs.In this thesis, a reliable power-efficient hybrid architecture employing...
Evaluating the Energy Consumption of Fault-Tolerance Mechanisms In Processors Implemented on Sram-Based Fpgas
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. The soft errors vulnerability of SRAM-based FPGAs limits their usage in safety-critical applications. Moreover, the rate of multiple soft errors increases due to the feature size reduction. Hence, this issue becomes a challenge against reliability of the implemented circuit on SRAM-based FPGAs. Appealing to specifics such as low cost and re-configurability in SRAM based FPGAs provide this ability to change implemented design remotely. This advantage is not negligible in safety critical...
An RT-Level Low Power Design Technique for Digital Circuits Implemented on FPGAs
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
RT-level techniques are one of the most important categories of techniques employed for decreasing power consumption in digital systems. These techniques are usually applied in the HDL description of the system, however some of them are applicable automatically by the synthesis tools. Some of the most commonly used RT-level techniques include Operand isolation, Clock gating, Concurrency & Redundancy, Pre-computation and Pipeline for low power. However these techniques have been mostly employed in ASIC designs, and FPGAs have scarcely been addressed. Application of these techniques on FPGAs might need special considerations, since resources on FPGAs are inherently different than their ASIC...
Improving Resolution in Millimeter-Wave Imaging Systems
, M.Sc. Thesis Sharif University of Technology ; Shabany, Mahdi (Supervisor) ; Kavehvash, Zahra ($item.subfieldsMap.e)
Abstract
Nowadays, millimeter-wave imaging is widely used in security and medical applications. The growing threat from terrorist attacks is driven research on novel ways to enhance security inspection systems. Millimeter-wave imaging not only is an effective option of penetrating into dielectric materials including cloth, but also provides suitable imaging resolution. Moreover, millimeter-wave imaging is capable of identifying different materials making it a promising option for concealed weapon detection. In spite of X-ray, millimeter-wave imaging is non-ionizing, allowing for non-invasive imaging. In this thesis, first we investigate different millimeter-wave imaging systems and reconstruction...
Performance Evaluation of Physical Unclonable Functions and Proposing a Scheme on FPGA
, M.Sc. Thesis Sharif University of Technology ; Bayat-Sarmadi, Siavash (Supervisor)
Abstract
In recent years, in addition to traditional cryptographic blocks, a hardware blocks in this work namely PUF, has been used mostly for chip ID generation, authentication and so on. In this work we study recent proposed PUFs and their implementations on FPGA, and the measurement of quality metrics on them. Some of most important characteristics of PUFs are unpredictability, reliability, number of challenge response pairs and area. According to experiments that have been performed in this study and also according to previous work, one high-quality PUF in term of uniqueness and reliability is Ring Oscillator PUF. However, the disadvantage of this PUF is small number of challenge and response...
Design and Implementation of a Tunable Frequency Channelizer on FPGA
, M.Sc. Thesis Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor)
Abstract
Nowdays, many of communication systems working together. The fist part of each communication system is related to separating a desired part of system input signal. This is called channelisation. Channelization is a process where single, few, or all channels from a certain frequency band are separated for further processing. The separation of single channel is usually done by down-conversion followed by filtering and optional sample-rate conversion. A straightforward implementation for multi channel sepration, which is also the traditional implementation of wideband channelizer, is to simply use a single-channel channelizer for each channel. A few applications require that an input signal be...
Hardware Implementation of Spiking Neural Networks
, M.Sc. Thesis Sharif University of Technology ; Shabany, Mahdi (Supervisor) ; Hashemi, Matin (Co-Supervisor)
Abstract
Spiking neural networks (SNNs) are third generation of neural networks. Similar to traditional neural networks, SNNs are comprised neurons. However, not only structure but also information processing is inspired by animal neural systems. SNNs can be called the most similar networks to animal neural systems. In such networks, the information is processed based on propagation of spike signals through the network. The type of data flow in these networks leads to being low-power when they are implemented on hardware. Therefore,there has been a upward trend in hardware implementation of them, like their FPGA implementations, for applications such as Big Data and Machine Learning. In this thesis,...