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field-programmable-gate-array--fpga
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Total 167 records
Blokus Duo game on FPGA
, Article roceedings - 17th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2013 ; 2013 , Pages 149-152 ; 9781479905621 (ISBN) ; Taram, M. K ; Eskandari, N ; Sharif University of Technology
IEEE Computer Society
2013
Abstract
There are a number of Artificial In elligence (AI) algorithms for implementation of 'Blokus Duo' game. We needed an implementation on FPGA, and moreover, the design had to respond under a given time constraint. In this paper we examine some of these algorithms and propose a heuristic algorithm to solve the problem by considering intelligence, time constraint and FPGA implementation limitations
A sigma-delta analog to digital converter based on iterative algorithm
, Article Eurasip Journal on Advances in Signal Processing ; Volume 2012, Issue 1 , 2012 ; 16876172 (ISSN) ; Ghorbani, M ; Marvasti, F ; Sharif University of Technology
2012
Abstract
In this article, we present a new iterative algorithm aimed at improving the performance of the sigma-delta analog to digital (A/D) converter. We subject the existing sigma-delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma-delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to...
Single fault reliability analysis in FPGA implemented circuits
, Article Proceedings - International Symposium on Quality Electronic Design, ISQED, 19 March 2012 through 21 March 2012 ; March , 2012 , Pages 49-56 ; 19483287 (ISSN) ; 9781467310369 (ISBN) ; Mohammadi, K ; Attarsharghi, P ; Sharif University of Technology
2012
Abstract
Reliability analysis in FPGA implementation of logic circuits is an important issue in designing fault tolerant systems for faulty environments. In this paper an analytical method is developed for analyzing such systems. This method is based on signal probability propagation of faults from the location of appearance to final outputs of circuit. Single fault model is used for the faults occurred in routes and LUTs. In addition reconvergent fan-outs are handled using 16 correlation coefficients propagation approach. Experimental results show a good agreement between this method and Monte Carlo method for reliability analysis of MCNC benchmarks
Implementation and hardware in the loop verification of five-leg converter control system on a FPGA
, Article IECON Proceedings (Industrial Electronics Conference), 7 November 2011 through 10 November 2011, Melbourne, VIC ; 2011 , Pages 4015-4020 ; 9781612849720 (ISBN) ; Zolghadri, M. R ; Poure, P ; Saadate, S ; Sharif University of Technology
2011
Abstract
FPGAs are interesting choices for control of power electronics converters and electrical drives. In this paper, implementation of the control method of a reduced switch- count five-leg converter is carried out. Two PWM methods are studied. For verification of the implemented controller in a practical manner, without risking the damaging of the real system, "FPGA in the loop" experiments are performed. It is shown that using the proposed methodology, FPGA implementation and verification is fast and effective. The provided results show the high performance of the implemented controller on the FPGA, therefore the feasibility and suitability of the FPGA for this application is approved
New configuration memory cells for FPGA in nano-scaled CMOS technology
, Article Microelectronics Journal ; Volume 42, Issue 11 , 2011 , Pages 1187-1207 ; 00262692 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2011
Abstract
In nano-scaled CMOS technology, the reduction of soft error rate and leakage current are the most important challenges in designing Field Programmable Gate Arrays (FPGA). To overcome these challenges, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents three new low-leakage and hardened configuration memory cells for nano-scaled CMOS technology. These cells are completely hardened when zeros are stored in the cells and cannot flip from particle strikes at the sensitive cell nodes. These cells retain their data with...
An efficient reconfigurable architecture by characterizing most frequent logic functions
, Article 25th International Conference on Field Programmable Logic and Applications, FPL 2015, 2 September 2015 through 4 September 2015 ; Sept , 2015 , Page(s): 1 - 6 ; 9780993428005 (ISBN) ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity...
A FPGA based time analyser for stochastic methods in experimental physics
, Article Instruments and Experimental Techniques ; Volume 58, Issue 3 , May , 2015 , Pages 350-358 ; 00204412 (ISSN) ; Khalafi, H ; Vosoughi, N ; Khakshournia, S ; Sharif University of Technology
Maik Nauka Publishing / Springer SBM
2015
Abstract
A two-channel time analyser data acquisition system is developed for analysis of stochastic processes of random time interval pulses. The system is implemented on a typical low cost FPGA device. Two stochastic processes of nuclear interactions can be recorded by the system independently without any inter-channel dead time behaviour. The experimental results without any hardware based data reduction are transferred to the computer to perform arbitrary post analysis of the data using powerful software engineering tools to estimate the statistical properties of the processes. The performance of the system is verified experimentally. The maximum time digitization period and the minimum channel...
A fine-grained configurable cache architecture for soft processors
, Article 18th CSI International Symposium on Computer Architecture and Digital Systems, 7 October 2015 through 8 October 2015 ; 2015 ; 9781467380232 (ISBN) ; Mirzazad Barijough, K ; Goudarzi, M ; Pourmohseni, B ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
The ever increasing density and performance of FPGAS, has increased the importance and popularity of soft processors. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this paper, a novel cache architecture, primarily aimed at soft processors, is proposed to address the variable access demands of applications, through dynamically configurable line-associativity, with no memory overhead. The FPGA implementation of the proposed architecture achieves an average miss count...
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs
, Article 26th International Conference on Field-Programmable Logic and Applications, FPL 2016, 29 August 2016 through 2 September 2016 ; 2016 ; 9782839918442 (ISBN) ; Omidi, B ; Amrouch, H ; Henkel, J ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration...
A fault tolerant parallelism approach for implementing High-throughput pipelined advanced encryption standard
, Article Journal of Circuits, Systems and Computers ; Volume 25, Issue 9 , 2016 ; 02181266 (ISSN) ; Hessabi, S ; Sharif University of Technology
World Scientific Publishing Co. Pte Ltd
2016
Abstract
Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement...
A low-latency QRD-RLS architecture for high-throughput adaptive applications
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 63, Issue 7 , 2016 , Pages 708-712 ; 15497747 (ISSN) ; Bagherzadeh, J ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
A novel architecture for QR decomposition-based recursive least squares is presented. It offers low latency for applications where the channel equalization and adaptive filtering are mandatory. This approach reduces the computations by rewriting the equations in a manner that lets intense hardware resource sharing by reusing similar values in different computations. Moreover, precision range conversion allows for combining complex operations such as root square and division with minimum effect on the overall quantization error. Hence, an efficient lookup table-based solution has highly enhanced the performance of the design by 2.7 times with respect to the previous works
A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era
, Article 20th Design, Automation and Test in Europe, DATE 2017, 27 March 2017 through 31 March 2017 ; 2017 , Pages 1342-1347 ; 9783981537093 (ISBN) ; Khaleghi, B ; Asadi, H ; ACM Special Interest Group on Design Automation (ACM SIGDA); Electronic System Design Alliance (ESDA); et al.; European Design and Automation Association (EDAA); European Electronic Chips and Systems Design Initiative (ECSI); IEEE Council on Electronic Design Automation (CEDA) ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present a Power gating Switch Box Architecture (PESA) for routing network of SRAM-based FPGAs to overcome the obstacle for further device integration. In the proposed architecture, by exploring various patterns of used multiplexers in switch boxes, we employ a configurable controller to turn off unused...
An efficient low-latency point-multiplication over curve25519
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 10 , 2019 , Pages 3854-3862 ; 15498328 (ISSN) ; Bayat Sarmadi, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
The elliptic curve cryptography (ECC) has gained attention mainly due to its lower complexity compared to other asymmetric methods while providing the same security level. The most performance critical operation in ECC is the point multiplication. Thus, its efficient implementation is desirable. One of the most secure and lightweight ECC curves, which satisfies all standard security criteria, is the Curve25519. In this paper, a low latency Karatsuba-Ofman-based field multiplier (KOM) and an efficient point multiplication over Curve25519 have been proposed. The improvements have been achieved mainly due to the proposed low latency pipelined KOM and efficient scheduling of field operations....
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes
, Article 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, 15 July 2019 through 17 July 2019 ; Volume 2019-July , 2019 , Pages 615-620 ; 21593469 (ISSN) ; 9781538670996 (ISBN) ; Sadrosadati, M ; Pointner, S ; Wille, R ; Sarbazi Azad, H ; Technical Committee on VLSI (TCVLSI) of IEEE Computer Society (CS) ; Sharif University of Technology
IEEE Computer Society
2019
Abstract
Field-Programmable Gate Arrays (FPGAs) employ a significant amount of SRAM cells in order to provide a flexible routing architecture. While this flexibility allows for a rather easy realization of arbitrary functionality, the respectively required cells significantly increase the area and power consumption of the FPGA. At the same time, it can be observed that full routing flexibility is frequently not needed in order to efficiently realize the desired functionality. In this work, we are proposing an FPGA realization which focuses on what is needed and realizes only a subset of the possible routing options using what we call Turn-Restricted Switch-Boxes. While this may yield a slight...
Low-latency double point multiplication architecture using differential addition chain over GF( 2 m)
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 4 , 2019 , Pages 1465-1473 ; 15498328 (ISSN) ; Bayat-Sarmadi, S ; Mosanaei-Boorani, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5,...
Closing leaks: Routing against crosstalk side-channel attacks
, Article 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2020, 23 February 2020 through 25 February 2020 ; 2020 , Pages 197-203 ; Mirzargar, S. S ; Stojilović, M ; Sharif University of Technology
Association for Computing Machinery, Inc
2020
Abstract
This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some IPs are provided by trusted and some by untrusted sources. It suffices that a ring-oscillator based sensor is conveniently routed next to a signal that carries secret information (for instance, a cryptographic key), for this information to possibly get leaked. To address this security concern, we apply several different strategies and evaluate them on benchmark circuits from Verilog-to-Routing tool suite. Our experiments show that, for a...
Optimizing pipelines of trigonometric functions for FPGAs
, Article 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM, Victoria, BC, 22 August 2007 through 24 August 2007 ; 2007 , Pages 105-108 ; 1424411904 (ISBN); 9781424411900 (ISBN) ; Ebrahimi, H ; Sarbazi Azad, H ; Sharif University of Technology
2007
Abstract
Trigonometric functions are one of the most applicable functions in digital signal processing. In this paper, we propose two approaches for optimizing pipeline implementation of the CORDIC algorithm and compare it with other previous approaches. The proposed solutions are implemented on one of the Xilinx Virtex family's FPGAs. Our simulation results show that for high input bits, our approach is preferable to other existing approaches. ©2007 IEEE
Soft error mitigation in switch modules of SRAM-based FPGAs
, Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 141-144 ; 02714310 (ISSN) ; Miremadi, S. G ; Pradhan, D. K ; Mathew, J ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2007
Abstract
In this paper, we propose two techniques to mitigate soft error effects on the switch modules of SRAM-based FPGAs: 1) The first technique tolerates SEU-caused open errors based on a new programming method for SRAM-bits of switch modules, and 2) The second technique mitigates SEU-cause short errors in the switch modules based on a mixed programmable and hard-wired switch module structure in the FPGAs. The effects of these two techniques on the delay, area and power consumption for 20 MCNC benchmark circuits are achieved using a minor modification in VPR and T-VPack FPGA CAD tools. The experimental results show that he first technique increase reliability of connections of switch module up to...
Hardware architecture for supersingular isogeny diffie-hellman and key encapsulation using a fast montgomery multiplier
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 68, Issue 5 , 2021 , Pages 2042-2050 ; 15498328 (ISSN) ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Alivand, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2021
Abstract
Public key cryptography lies among the most important bases of security protocols. The classic instances of these cryptosystems are no longer secure when a large-scale quantum computer emerges. These cryptosystems must be replaced by post-quantum ones, such as isogeny-based cryptographic schemes. Supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE) are two of the most important such schemes. To improve the performance of these protocols, we have designed several modular multipliers. These multipliers have been implemented for all the prime fields used in SIKE round 3, on a Virtex-7 FPGA, showing a time and area-time product improvement of up to 60.1% and 64.5%,...
Shrinking FPGA static power via machine learning-based power gating and enhanced routing
, Article IEEE Access ; Volume 9 , 2021 , Pages 115599-115619 ; 21693536 (ISSN) ; Asadi, H ; Stojilovic, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2021
Abstract
Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA...