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    Design of a Strong Delay-based PUF for FPGA 6 Series Based Systems

    , M.Sc. Thesis Sharif University of Technology Babaei, Ehsan (Author) ; Haj Sadeghi, Khosro (Supervisor)
    Abstract
    There are three types of Slices in an FPGA, and based on the functionality of these slices, SliceM has the most features especially for designs based on shift registers, adders, and ROMs, and from all of the slices, 25% of them are SliceM. Among the earlier designs that are FPGA-based, Anderson PUF is that is classified as a weak delay-based PUF. In Anderson’s design there always should be atleast two SliceMs that their LUTs are configured as shift registers, the Andersons PUF in some FPGA Architecture especially Series 7 FPGAs, consumes two SliceMs and two other SliceLs, so practically we are using four of our precious slices. Rather than these, in series 6 FPGAs, the design should change... 

    High-Performance Architecture for Post-Quantum Cryptography Based on Elliptic Curve Isogeny

    , Ph.D. Dissertation Sharif University of Technology Farzam, Mohammad Hossein (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Public-key cryptography is vital to secure digital communication. The classic instances of these cryptosystems are insecure against large-scale quantum computers. As a result, post-quantum cryptography has emerged as a replacement, which includes different categories. Isogeny-based schemes are one of the promising candidates mainly because of their smaller public key length. Due to high computational cost of such schemes, efficient implementations are significantly important. In this thesis, we have presented various solutions at three different abstraction layers. At the lowest layer, which deals with modular arithmetic, two hardware architectures are presented to perform modular... 

    Hardware Implementation of Li-Fi System

    , M.Sc. Thesis Sharif University of Technology Sadeghi, Maryam (Author) ; Shabani, Mahdi (Supervisor) ; Kavehvash, Zahra (Co-Supervisor)
    Abstract
    Today, the “wireless” is used almost synonymously with radio-frequency (RF) technologies as a result of the wide-scale deployment and utilization of wireless RF devices and systems. The RF band ranges from 300 kHz to 300 GHz and its use is regulated by regional and international agencies. With the ever-growing popularity of data-heavy wireless communications, wireless products and services, the demand for RF spectrum is outstripping supply, which causes the spectrum congestion. Therefore, the time has come to seriously consider other viable options for wireless communication using the upper parts of the electromagnetic spectrum. In this way, the optical band which includes infrared, visible,... 

    Hardware Acceleration of Convolutional Neural Networks by Computational Prediction

    , M.Sc. Thesis Sharif University of Technology Sajjadi, Pegahsadat (Author) ; Bayatsarmadi, Siavash (Supervisor)
    Abstract
    Recently, Convolutional neural networks (CNNs) are widely used in many artificial intelligence applications such as image processing, speech processing and robotics. The neural networks superior accuracy comes at the cost of high computational complexity. Recent studies show that these operations can be performed in parallel. Therefore, as graphic processing units (GPUs) offer the best performance in terms of computational power and throughput, they are widely used to implement and accelerate neural networks. Nevertheless, the high price and power consumption of these processors have resulted in drawing more attraction towards Field-Programmable Arrays (FPGAs). In order to improve resource... 

    Hardware Acceleration of Deep Learning based Firewalls Using FPGA

    , M.Sc. Thesis Sharif University of Technology Fotovat, Amin (Author) ; Jahangir, Amir Hossein (Supervisor)
    Abstract
    In recent years, due to the drawback of rule-based firewalls in detecting unknown attacks, using neural networks has got more attention to be used in firewalls. As the computation load of neural networks are so much there is a need to decrease the processing time and power consumption as they are under load 24/7. Although there have been huge achievements in the usage of graphics processing units (which contain numerous processing cores) in neural networks, their high power consumption has made the scientists think about an alternative to implement neural networks. Field Programmable Gate Array (FPGA) is one of the most serious candidates to be used for implementing neural networks. The goal... 

    A Hardware-Software Partitioner for Deep Learning Algorithms

    , M.Sc. Thesis Sharif University of Technology Haghighi, Sepand (Author) ; Hessabi, Shahin (Supervisor)
    Abstract
    Deep learning, as a subdivision of machine learning, attempts to model high-level concepts by using a deep graph, consisting of several layers of linear and nonlinear transformations. Implementing these algorithms on hardware is a big challenge.¬This project offers a system in which various hardware methodologies can be used to implement deep learning algorithms side by side. The overall structure of the system consists of high-level programming interfaces for implementation and expression of machine learning algorithms by the user, which will be available as libraries in a high-level programming language such as Python, Ruby, and Julia. These interfaces allow the user to evaluate their... 

    Low-cost, Non-infrared, MRI-compatible Eye Tracker for Research

    , M.Sc. Thesis Sharif University of Technology Cherakhloo, Mahdi (Author) ; Ghazizadeh, Ali (Supervisor)
    Abstract
    Looking for eye paths is widely used in various research and even commercial areas, Eye trackers that are used commercially today do this by using infrared transmitters and receivers. As the speed and performance of the processors advanced, many efforts have been made to create an eye-tracking device using visible light without any movement restrictions for the subject, and efforts to increase the accuracy and speed of sampling are still ongoing; The initial methods proposed in this area are feature-based, but newer papers and researches have used Deep learning methods to do this. The commonly used methods for eye tracking in visible light are three main steps: 1. Fetching frames from the... 

    Protein Interaction Prediction Through Efficient FPGA and GPU Implementation

    , M.Sc. Thesis Sharif University of Technology Dehghan Nayeri, Ali (Author) ; Koohi, Somayyeh (Supervisor)
    Abstract
    Alignment of genetic sequences is a fundamental part of genetic and bio-science. Alignment of DNA and protein sequences has an effective role in accelerating and simplifying problems in Bioinformatics like predicting protein interactions. Smith-Waterman algorithm is a precise algorithm for performing local alignment, suffering from computation complexity. There are some implementations on CPU, GPU, and FPGA platforms in order to reduce the run time of this algorithm. FPGA implementation is considered because of low power consumption and high degree of parallelism. With using pipeline and hardware redundancy techniques, various architectures have been proposed and implemented. In the best... 

    Fault-resilient lightweight cryptographic block ciphers for secure embedded systems

    , Article IEEE Embedded Systems Letters ; Vol. 6, issue. 4 , 2014 , pp. 89-92 ; ISSN: 19430663 Mozaffari Kermani, M ; Tian, K ; Azarderakhsh, R ; Bayat Sarmadi, S ; Sharif University of Technology
    Abstract
    The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

    Networked adaptive non-linear oscillators: A digital synthesis and application

    , Article Circuits, Systems, and Signal Processing ; Vol. 34, Issue. 2 , 2014 , pp. 483-512 ; ISSN: 1531-5878 Maleki, M. A ; Ahmadi, A ; Makki, S. V. A. - D ; Soleimani, H ; Bavandpour, M ; Sharif University of Technology
    Abstract
    This paper presents a digital hardware implementation of a frequency adaptive Hopf oscillator along with investigation on systematic behavior when they are coupled in a population. The mathematical models of the oscillator are introduced and compared in sense of dynamical behavior by using system-level simulations based on which a piecewise-linear model is developed. It is shown that the model is capable to be implemented digitally with high efficiency. Behavior of the oscillators in different network structures to be used for dynamic Fourier analysis is studied and a structure with more precise operation which is also more efficient for FPGA-based implementation is implemented. Conceptual... 

    Towards dark silicon era in FPGAs using complementary hard logic design

    , Article Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 ; Sept , 2014 , pp. 1 - 6 ; ISBN: 9783000446450 Ahari, A ; Khaleghi, B ; Ebrahimi, Z ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

    Emerging non-volatile memory technologies for future low power reconfigurable systems

    , Article 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC ; 26-28 May , 2014 , pp. 1-2 ; 9781479958108 Ahari, A ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    Non-volatile memory (NVM) technologies are promising alternatives to traditional CMOS memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in reconfigurable systems such as Field-Programmable Gate Arrays (FPGAs). In this paper, we investigate the applicability of different NVM technologies for the configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). Quantitative analysis for various FPGA architectures using different memory technologies shows the benefits of the proposed scheme  

    A power-efficient reconfigurable architecture using PCM configuration technology

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2014 Ahari, A ; Asadi, H ; Khaleghi, B ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    Promising advantages offered by resistive NonVolatile Memories (NVMs) have brought great attention to replace existing volatile memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in Field-Programmable Gate Arrays (FPGAs). One major limitation of employing NVMs in FPGAs is significant power and area overheads imposed by the Peripheral Circuitry (PC) of NVM configuration bits. In this paper, we investigate the applicability of different NVM technologies for configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). The proposed PCM-based architecture has been... 

    Development of an embedded FPGA-based data acquisition system dedicated to zero power reactor noise experiments

    , Article Metrology and Measurement Systems ; Vol. 21, issue. 3 , Aug , 2014 , p. 433-446 ; 08608229 Arkani, M ; Khalafi, H ; Vosoughi, N ; Sharif University of Technology
    Abstract
    An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit × 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure... 

    Fault tolerant operation of single-ended non-isolated DC-DC converters under open and short-circuit switch faults

    , Article 2013 15th European Conference on Power Electronics and Applications, EPE 2013 ; 2013 ; ISBN: 9781479901166 Jamshidpour, E ; Shahbazi, M ; Poure, P ; Gholipour, E ; Saadate, S ; Sharif University of Technology
    2013
    Abstract
    Fault tolerant operation of single-ended non-isolated DC-DC converters used in embedded and safety critical applications is mandatory to guaranty service continuity. This paper proposes a new, fast and efficient FPGA-based open and short-circuit switch fault diagnosis asssociated to fault tolerant converter topology. The results of Hardware-In-the-Loop and experimental tests are presented and discussed  

    Fast short circuit power switch fault detection in cascaded H-bridge multilevel converter

    , Article IEEE Power and Energy Society General Meeting ; 2013 ; 19449925 (ISSN); 9781479913039 (ISBN) Shahbazi, M ; Zolghadri, M. R ; Poure, P ; Saadate, S ; Sharif University of Technology
    2013
    Abstract
    Multilevel converters are being widely used in a large number of power electronics applications. Due to the increased number of switching devices, they are more likely to have faults in their switches than the conventional converters. In order to have a balanced operation after a short circuit power switch fault occurrence, it is necessary to detect the fault location. In this paper, a fast power switch fault detection method is presented to identify the fault location. This method only needs one additional voltage sensor per phase, and is faster compared to most of the existing methods. Also it is easy for implementation on a FPGA chip. The proposed method is verified by computer... 

    Efficient implementation of real-time ECG derived respiration system using cubic spline interpolation

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 1083-1086 ; 02714310 (ISSN) ; 9781467357609 (ISBN) Shayei, A ; Ehsani, S. P ; Shabany, M ; Sharif University of Technology
    2013
    Abstract
    Monitoring the respiratory signal is crucial in many medical applications. Traditional methods for the respiration measurement are normally based on measuring the volume of air inhaled and exhaled by lungs (like spirometer) or oxygen saturation in blood. However, these methods have numerous challenges including their high cost and not being accessible in some cases. In this paper, an algorithm for deriving the respiratory signal from ECG signal is proposed, which is based on other proposed algotithms. This algorithm uses the cubic spline interpolation (CSI) of R-waves in ECG to derive the respiratory signal. The CSI algorithm is made efficient with respect to ECG features in order to reduce... 

    Low-leakage soft error tolerant port-less configuration memory cells for FPGAs

    , Article Integration, the VLSI Journal ; Volume 46, Issue 4 , September , 2013 , Pages 413-426 ; 01679260 (ISSN) Azizi Mazreah, A ; Manzuri Shalmani, M. T ; Sharif University of Technology
    2013
    Abstract
    As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When... 

    FPGA-based fast detection with reduced sensor count for a fault-tolerant three-phase converter

    , Article IEEE Transactions on Industrial Informatics ; Volume 9, Issue 3 , 2013 , Pages 1343-1350 ; 15513203 (ISSN) Mahmoud, M ; Philippe, P ; Shahrokh, S ; Mohammad Reza, M. R ; Sharif University of Technology
    2013
    Abstract
    Fast fault detection (FD) and reconfiguration is necessary for fault tolerant power electronic converters in safety critical applications to prevent further damage and to make the continuity of service possible. The aim of this study is to minimize the number of the used additional voltage sensors in a fault tolerant three-phase converter. In this paper, first a practical implementation of a very fast FD scheme with reduced sensor number is discussed. Then, an optimization in this scheme is also presented to decrease the detection time. For FD, special time and voltage criterion are applied to observe the error in the estimated phase-to-phase voltages for a specific period of time. The... 

    Open-and short-circuit switch fault diagnosis for nonisolated DC-DC converters using field programmable gate array

    , Article IEEE Transactions on Industrial Electronics ; Volume 60, Issue 9 , October , 2013 , Pages 4136-4146 ; 02780046 (ISSN) Shahbazi, M ; Jamshidpour, E ; Poure, P ; Saadate, S ; Zolghadri, M. R ; Sharif University of Technology
    2013
    Abstract
    Fault detection (FD) in power electronic converters is necessary in embedded and safety critical applications to prevent further damage. Fast FD is a mandatory step in order to make a suitable response to a fault in one of the semiconductor devices. The aim of this study is to present a fast yet robust method for fault diagnosis in nonisolated dc-dc converters. FD is based on time and current criteria which observe the slope of the inductor current over the time. It is realized by using a hybrid structure via coordinated operation of two FD subsystems that work in parallel. No additional sensors, which increase system cost and reduce reliability, are required for this detection method. For...