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field-programmable-gate-arrays--fpga
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Error propagation analysis using FPGA-based SEU-fault injection
, Article Microelectronics Reliability ; Volume 48, Issue 2 , 2008 , Pages 319-328 ; 00262714 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2008
Abstract
Error propagation analysis is one of the main objectives of fault injection experiments. This analysis helps designers to detect design mistakes and to provide effective mechanisms for fault tolerant systems. However, error propagation analysis requires that the chosen fault injection technique provides a high degree of observability (i.e., the ability to observe the internal values and events of a circuit after a fault is injected). Simulation-based fault injection provides a high observability adequate for error propagation analysis. However, the performance of the simulation-based technique is inadequate to handle today's hardware complexity. As an alternative, FPGA-based fault injection...
SEU-mitigation placement and routing algorithms and their impact in SRAM-based FPGAs
, Article 8th International Symposium on Quality Electronic Design, ISQED 2007, San Jose, CA, 26 March 2007 through 28 March 2007 ; 2007 , Pages 380-385 ; 0769527957 (ISBN); 9780769527956 (ISBN) ; Miremadi, S. G ; Pradhan, D. K ; Mathew, J ; Sharif University of Technology
2007
Abstract
In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility...
A solution to single point of failure using voter replication and disagreement detection
, Article 2nd IEEE International Symposium on Dependable, Autonomic and Secure Computing, DASC 2006, Indianapolis, IN, 29 September 2006 through 1 October 2006 ; 2006 , Pages 171-176 ; 0769525393 (ISBN); 9780769525396 (ISBN) ; Miremadi, S. Gh ; Javadtalab, A ; Fazeli, M ; Farazmand, N ; Sharif University of Technology
2006
Abstract
This paper suggests a method, called distributed voting, to overcome the problem of the single point of failure in a TMR system used in robotics and industrial control applications. It uses time redundancy and is based on TMR with disagreement detector feature. This method masks faults occurring in the voter where the TMR system can continue its function properly. The method has been evaluated by injecting faults into Vertex2Pro and Vertex4 Xilinx FPGAs. An analytical evolution is also performed. The results of both evaluation approaches show that the proposed method can improve the reliability and the mean time to failure (MTTF) of a TMR system by at least a factor of (2-R v(t)) where Rv(t)...
Isogeny diffie-hellman and key encapsulation using a customized pipelined montgomery multiplier
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; 2021 ; 15498328 (ISSN) ; Bayat-Sarmadi, S ; Mosanaei-Boorani, H ; Alivand, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2021
Abstract
We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times...
Investigation of transient effects on FPGA-based embedded systems
, Article ICESS 2005 - 2nd International Conference on Embedded Software and Systems, Xian, 16 December 2005 through 18 December 2005 ; Volume 2005 , 2005 , Pages 231-236 ; 0769525121 (ISBN); 9780769525129 (ISBN) ; Miremadi, S. G ; Zarandi, H. R ; Sharif University of Technology
2005
Abstract
In this paper, we present an experimental evaluation of transient effects on an embedded system which uses SRAM-based FPGAs. A total of 7500 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD) and a simple 8-bit microprocessor was implemented on the FPGA as the testbench. The results show that nearly 64 percent of faults cause system failures and about 63 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE
A hardware approach to concurrent error detection capability enhancement in COTS processors
, Article 11th Pacific Rim International Symposium on Dependable Computing, PRDC 2005, Changsha, Hunan, 12 December 2005 through 14 December 2005 ; Volume 2005 , 2005 , Pages 83-90 ; 0769524923 (ISBN); 9780769524924 (ISBN) ; Miremadi, S. G ; Sharif University of Technology
2005
Abstract
To enhance the error detection capability in COTS (commercial off-the-shelf) -based design of safety-critical systems, a new hardware-based control flow checking (CFC) technique will be presented. This technique, Control Flow Checking by Execution Tracing (CFCET), employs the internal execution tracing features available in COTS processors and an external watchdog processor (WDP) to monitor the addresses of taken branches in a program. This is done without any modification of application programs, therefore, the program overhead is zero. The external hardware overhead is about 3.5% using an Altera Flex 10K30 FPGA. For different workload programs, the execution time overhead and the error...
Experimental evaluation of transient effects on SRAM-based FPGA chips
, Article 17th 2005 International Conference on Microelectronics, ICM 2005, Islamabad, 13 December 2005 through 15 December 2005 ; Volume 2005 , 2005 , Pages 251-255 ; 0780392620 (ISBN); 9780780392625 (ISBN) ; Miremadi, S. G ; Zarandi, H. R ; Sharif University of Technology
2005
Abstract
This paper presents an experimental evaluation of transient effects on SRAM-based FPGAs. A total of 9000 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD). The results show that nearly 60 percent of faults cause system failures and about 58 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE
Networked adaptive non-linear oscillators: A digital synthesis and application
, Article Circuits, Systems, and Signal Processing ; Vol. 34, Issue. 2 , 2014 , pp. 483-512 ; ISSN: 1531-5878 ; Ahmadi, A ; Makki, S. V. A. - D ; Soleimani, H ; Bavandpour, M ; Sharif University of Technology
Abstract
This paper presents a digital hardware implementation of a frequency adaptive Hopf oscillator along with investigation on systematic behavior when they are coupled in a population. The mathematical models of the oscillator are introduced and compared in sense of dynamical behavior by using system-level simulations based on which a piecewise-linear model is developed. It is shown that the model is capable to be implemented digitally with high efficiency. Behavior of the oscillators in different network structures to be used for dynamic Fourier analysis is studied and a structure with more precise operation which is also more efficient for FPGA-based implementation is implemented. Conceptual...
FPGA-based fast detection with reduced sensor count for a fault-tolerant three-phase converter
, Article IEEE Transactions on Industrial Informatics ; Volume 9, Issue 3 , 2013 , Pages 1343-1350 ; 15513203 (ISSN) ; Philippe, P ; Shahrokh, S ; Mohammad Reza, M. R ; Sharif University of Technology
2013
Abstract
Fast fault detection (FD) and reconfiguration is necessary for fault tolerant power electronic converters in safety critical applications to prevent further damage and to make the continuity of service possible. The aim of this study is to minimize the number of the used additional voltage sensors in a fault tolerant three-phase converter. In this paper, first a practical implementation of a very fast FD scheme with reduced sensor number is discussed. Then, an optimization in this scheme is also presented to decrease the detection time. For FD, special time and voltage criterion are applied to observe the error in the estimated phase-to-phase voltages for a specific period of time. The...
Fast detection of open-switch faults with reduced sensor count for a fault-tolerant three-phase converter
, Article 2011 2nd Power Electronics, Drive Systems and Technologies Conference, PEDSTC 2011 ; 2011 , Pages 546-550 ; 9781612844213 (ISBN) ; Zolghadri, M ; Poure, P ; Saadate, S ; Sharif University of Technology
Abstract
Fast fault detection and reconfiguration is necessary in power electronic converters in lots of applications to prevent further damage and to make possible the continuity of service. In this paper a very fast fault detection scheme is presented that minimizes the use of voltage sensors. A fault tolerant topology is studied. Control and fault detection system are implemented on a single FPGA and hardware in the loop experiments are performed to evaluate the detection scheme, the digital controller and the structure
Open-circuit switch fault tolerant wind energy conversion system based on six/five-leg reconfigurable converter
, Article Electric Power Systems Research ; Volume 137 , 2016 , Pages 104-112 ; 03787796 (ISSN) ; Saadate, S ; Poure, P ; Zolghadri, M ; Sharif University of Technology
Elsevier Ltd
2016
Abstract
In this paper, an FPGA-controlled fault tolerant back-to-back converter for DFIG-based wind energy conversion application is studied. Before an open-circuit failure in one of the semiconductors, the fault tolerant converter operates as a conventional back-to-back six-leg one. After the fault occurrence in one of the switches, the converter will continue its operation with the remaining five healthy legs. Design, implementation, simulation and experimental verification of a reconfigurable control strategy for the fault tolerant six/five leg converter used in wind energy conversion are discussed. The proposed reconfigurable control strategy allows the uninterrupted operation of the converter...
Quick diagnosis of short circuit faults in cascaded H-bridge multilevel inverters using FPGA
, Article Journal of Power Electronics ; Volume 17, Issue 1 , 2017 , Pages 56-66 ; 15982092 (ISSN) ; Zolghadri, M. R ; Rodriguez, J ; Shahbazi, M ; Oraee, H ; Lezana, P ; Schmeisser, A. U ; Sharif University of Technology
Korean Institute of Power Electronics
2017
Abstract
Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to “0” is detected as the faulty cell. Furthermore, consideration of generating the active...
Digital Design and Implementation of a Multilevel OCDMA System
, M.Sc. Thesis Sharif University of Technology ; Salehi, Javad (Supervisor)
Abstract
Optical Wireless Communication is believed to have a great potential in establishing point to point connection and have attracted an unexpected growth in research , applications and market. Furthermore, Optical wireless systems have recently emerged as a new means of communication, especially in places where electromagnetic interferences is of utmost concern such as in passenger planes and hospitals and in other communications applications where cost could is of concern. In this thesis we build upon previously introduced wireless optical code-division multiple –access communication. In the context of an OCDMA system we begin our study by considering synchronization circuit via a...
Analysis, Design and Implementation of a Low Power and High Speed Sound Source Localizer
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor) ; Gholampour, Iman (Supervisor)
Abstract
Throughout localization algorithms, sound source localization has received much interest using microphone array. Applications like tracking and determining angle of acoustic signal arrival have been combined with array processing techniques in the previous decade. Distributed micro sensor array have been suggested for a wide range of nowaday’s localization algorithms. The major goals are monitoring the environment, distinction, and pursue some phenomenon. This type of networks can be utilized for military application in tracking acoustic sources. Today’s advancement in technology allows implementation of the ultra low cost and low power integrated circuit for such application in the form of...
Reconfigurable Architecture For Cryptanalysis Applications
, M.Sc. Thesis Sharif University of Technology ; Jahangir, Amir Hossein (Supervisor)
Abstract
Nowadays, the significance of securing data and information is undeniable. Cryptography is being used to provide data security. In addition, cryptanalysis is required to evaluate the effectiveness of cryptography methods, and hence, it is an essential concept for securing data. In general, the cryptography functions shall be designed in a way to impose a high load of time-intensive operations to prevent an adversary from accessing the main data from the encrypted data. As a result, cryptography and cryptanalysis algorithms need high performance computations. So far, a number of methods have been proposed to support the required performance. These methods include: distributed computing and...
High Speed Digital Receiver, Design and Implementation
, M.Sc. Thesis Sharif University of Technology ; Sanaei, Esmaeel (Supervisor) ; Pezeshk, Amir Mansoor (Supervisor)
Abstract
Nowadays, increasingly improvements in the digital technology and the advantages of using digital signal processing methods lead engineers to use digital signal processing instead of analog processing in variant domains. However, speed limitations in analog to digital converters (ADCs) and data transfer ports prevent its penetration to high frequency signals region. In this thesis, an Instantaneous Frequency Measurement (IFM) system that can measure frequency in the range of 2-18 GHz is implemented fully digital (DIFM) on FPGA. To do so, monobit sampling technique with the sampling rate of 10 GHz is selected, and GTX high speed serial port is configured to transfer digital data into FPGA....
Improving Energy Efficiency in Multi-processor Soft-Core Systems Using System-level Techniques
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
The ever increasing density and performance of FPGAs, has increased the importance and popularity of soft processors. One major research concern in this regard lays in the field of energy efficiency of the system on FPGA. This work is particularly focused on the energy efficiency of multiprocessor structures on FPGA using system level techniques. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy, i.e. caches. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this thesis, two novel cache architecture, primarily aimed at...
Exploiting Bandpass Sampling and Compressed Sensing Alghorithms for RF to Digital Direct Conversion
, M.Sc. Thesis Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor) ; Pezeshk, Amir Mansour (Co-Advisor)
Abstract
The target of reconnaissance receivers is to detect radio frequencies and pulses present in the environment and extracting their characteristics. To receive the signals in the range of 2 to 18 GHz, different receptors can be used. Each receptor has its specific aplications, advantages and disadvantages. In this project, we proposed a receptor scheme with the following features: 1-simple hardware, 2-ability to detect simultaneous signals, 3-hundred percent probability of intercept (POI), 4-high input bandwidth and 5-rapid threat detection. To have such a receptor, we should move data processing parts of receptor to digital domain as much as possible, and reduce the amount of analog...
Managing Shared Use of an FPGA-based Accelerator among Virtual Machines
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Using accelerators inside high speed servers can reduce execution time of applications and total power usage of the system. Sharing accelerator between virtual machines of a server decrease both cost and power, however it won’t provide the gained speedup of using dedicated accelerator for each virtual machines. Creation of an appropriate set of accelerators required for virtual machines, management of accesses to the accelerator, prioritizing and scheduling of requests and reconfiguration type of accelerator are the most important challenges that this project has been dealt with. The main objective of this project is implementing the necessary infrastructure to share an FPGA-based...
Design and Implementation Real-Time Simulator for CHB Converter using FPGA
, M.Sc. Thesis Sharif University of Technology ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
With development of power electronic science and with the existence of different power electronic converters in this field, the need for improving their operation and the fault detection methods of these converters, the need for simulation and test of them is strong felt. However, experimental constrain such as damage risks, reliability, costs, and so on obviate the need for making the converter and the need for testing it and its controller. Accordingly, we do the testing on a special platform for Real-Time simulation.Control/protection platform needs to be tested and its functionality should be verified prior to installation and commissioning.Testing in theReal-Time simulator environment...