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    A Power Efficient Routing Architecture for Reconfigurable Device

    , M.Sc. Thesis Sharif University of Technology Zandieh, Mohsen (Author) ; Asadi, Hossein (Supervisor)
    Abstract
    FPGA is a suitable substrate for implementation of embedded systems, mobiles, and hand-held devices due to cost reduction for \emph{Non-Recurring Engineering (NRE)}, short time to market, design flexibility, and reprogramming capability. Significant downscaling of CMOS technology feature size has led to static power growth rate, which is a limiting factor in further scaling. Previous studies aimed at reducing power consumption, mainly have focused on the power consumption of logical resources. However, proposing a low power architecture in routing network affects the power consumption of FPGAs significantly, because of the dominant power consumption in the routing network. This thesis... 

    An Efficient Reconfigurable Architecture to Speed up Machine Learning Algorithms

    , M.Sc. Thesis Sharif University of Technology Nezamfar, Elmira (Author) ; Asadi, Hossein (Supervisor)
    Abstract
    Machine learning algorithms are achieving state-of-the-art performance in many various applications such as image processing, machine vision, speech recognition, diagnosis diseases, robotics, military, and aerospace. For decades, the usage of machine learning algorithms especially Neural Network Algorithms (NNA) has been restricted due to their complexity and high computation time of available inefficient hardwares. Although advances in technology and the emergence of powerful processors has increased the usage of NNAs, especially Deep Neuaral Networks (DNNs), the research gap in machine learning hardware platform with high performance as well as high energy efficiency is still remaining.... 

    FPGA-Based Implementation of Deep Learning Accelerator with Concentration on Intrusion Detection Systems

    , M.Sc. Thesis Sharif University of Technology Fard, Ebrahim (Author) ; Jahangir, Amir Hossein (Supervisor)
    Abstract
    Intrusion Detection System (IDS) is an equipment destined to provide computer networks security. In recent years, Machine Learning and Deep Neural Network (DNN) methods have been considered as a way to detect new network attacks. Due to the huge amounts of calculations needed for these methods, there is a need for high performance and parallel or specific processors, such as Application Specific Integrated Circuit (ASIC), Graphical Processor Unit (GPU) and Field-Programmable Gate Array (FPGA). The latter seems more suitable than others due to its higher configurability and lesser power consumption. The goal of this study is the acceleration of a DNN-based IDS on FPGA. In this study, which is... 

    Design of Monitoring and Control System for Ion Implanter Gases

    , M.Sc. Thesis Sharif University of Technology Baharian, Hossein (Author) ; Rashidian, Bijan (Supervisor)
    Abstract
    Very dangerous gases are used in ion implanter machines. Opening and closing the valves of these gases can be very dangerous. In this project, these valves are inspected, monitored and opened and closed from a safe distance. To do this, we must monitor and control the above system by using the latest and most efficient technologies available and with the least delay. For accurate and precise monitoring, clear images should be obtained from the location and changes should be detected, and the device can be controlled very quickly with the necessary commands. To do this, one must have an accurate and comprehensive knowledge of processors and communication protocols, and also pay attention to... 

    Design and Efficient Implementation of Equalizer and Synchronizer Block in Recent Telecommunication Links Standards

    , M.Sc. Thesis Sharif University of Technology Zeighami, Amir Mahdi (Author) ; Shabany, Mahdi (Supervisor)
    Abstract
    Today, telecommunication links transmit information wirelessly at high rates; The transmission channel is not ideal and the transmitted signal undergoes changes in the channel and then reaches the receiver; Also, the processing blocks in the transmitter and receiver are not completely similar and ideal; These two factors make it difficult for the receiver to recover the transmitted information and actually receives a signal that bears little resemblance to the transmitted signal. The most important effect that the channel has on the transmitted signal is due to the multi-path of the channel between the transmitter and the receiver, which causes a signal to reach the receiver through the... 

    Fast Alignment-free Protein Comparison Approach based on FPGA Implementation

    , M.Sc. Thesis Sharif University of Technology Abdosalehi, Azam Sadat (Author) ; Koohi, Somayyeh (Supervisor)
    Abstract
    Protein, as the functional unit of the cell, plays a vital role in its biological function. With the advent of advanced sequencing techniques in recent years and the consequent exponential growth of the number of protein sequences extracted from diverse biological samples, their analysis, comparison, and classification have faced a considerable challenge. Existing methods for comparing proteins divide into two categories: methods based on alignment and alignment-free. Although alignment-based methods are among the most accurate methods, they face inherent limitations such as poor analysis of protein groups with low sequence similarity, time complexity, computational complexity, and memory... 

    Evaluating Effect of Number Representations on the Accuracy of Convolutional Neural Networks

    , M.Sc. Thesis Sharif University of Technology Aghamohammadi Bonab, Yeganeh (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Convolutional Neural Networks are a kind of neural network applicable in machine vision and image processing. The accuracy of these networks is dependent on different features such as network size network and input size. Today, researchers are improving the accuracy of neural networks by increasing their size. As a result, networks' computation will increase as well. The bigger the size of the neural network, the harder its hardware implementation. One of the proposed solutions to overcome this issue is to change the number representation while preserving the network accuracy. It's challenging to implement floating-point computation on hardware as it consumes a high amount of power and... 

    Design of a Strong Delay-based PUF for FPGA 6 Series Based Systems

    , M.Sc. Thesis Sharif University of Technology Babaei, Ehsan (Author) ; Haj Sadeghi, Khosro (Supervisor)
    Abstract
    There are three types of Slices in an FPGA, and based on the functionality of these slices, SliceM has the most features especially for designs based on shift registers, adders, and ROMs, and from all of the slices, 25% of them are SliceM. Among the earlier designs that are FPGA-based, Anderson PUF is that is classified as a weak delay-based PUF. In Anderson’s design there always should be atleast two SliceMs that their LUTs are configured as shift registers, the Andersons PUF in some FPGA Architecture especially Series 7 FPGAs, consumes two SliceMs and two other SliceLs, so practically we are using four of our precious slices. Rather than these, in series 6 FPGAs, the design should change... 

    Hardware Acceleration of Deep Learning based Firewalls Using FPGA

    , M.Sc. Thesis Sharif University of Technology Fotovat, Amin (Author) ; Jahangir, Amir Hossein (Supervisor)
    Abstract
    In recent years, due to the drawback of rule-based firewalls in detecting unknown attacks, using neural networks has got more attention to be used in firewalls. As the computation load of neural networks are so much there is a need to decrease the processing time and power consumption as they are under load 24/7. Although there have been huge achievements in the usage of graphics processing units (which contain numerous processing cores) in neural networks, their high power consumption has made the scientists think about an alternative to implement neural networks. Field Programmable Gate Array (FPGA) is one of the most serious candidates to be used for implementing neural networks. The goal... 

    A Hardware-Software Partitioner for Deep Learning Algorithms

    , M.Sc. Thesis Sharif University of Technology Haghighi, Sepand (Author) ; Hessabi, Shahin (Supervisor)
    Abstract
    Deep learning, as a subdivision of machine learning, attempts to model high-level concepts by using a deep graph, consisting of several layers of linear and nonlinear transformations. Implementing these algorithms on hardware is a big challenge.¬This project offers a system in which various hardware methodologies can be used to implement deep learning algorithms side by side. The overall structure of the system consists of high-level programming interfaces for implementation and expression of machine learning algorithms by the user, which will be available as libraries in a high-level programming language such as Python, Ruby, and Julia. These interfaces allow the user to evaluate their... 

    Low-cost, Non-infrared, MRI-compatible Eye Tracker for Research

    , M.Sc. Thesis Sharif University of Technology Cherakhloo, Mahdi (Author) ; Ghazizadeh, Ali (Supervisor)
    Abstract
    Looking for eye paths is widely used in various research and even commercial areas, Eye trackers that are used commercially today do this by using infrared transmitters and receivers. As the speed and performance of the processors advanced, many efforts have been made to create an eye-tracking device using visible light without any movement restrictions for the subject, and efforts to increase the accuracy and speed of sampling are still ongoing; The initial methods proposed in this area are feature-based, but newer papers and researches have used Deep learning methods to do this. The commonly used methods for eye tracking in visible light are three main steps: 1. Fetching frames from the... 

    Fault-resilient lightweight cryptographic block ciphers for secure embedded systems

    , Article IEEE Embedded Systems Letters ; Vol. 6, issue. 4 , 2014 , pp. 89-92 ; ISSN: 19430663 Mozaffari Kermani, M ; Tian, K ; Azarderakhsh, R ; Bayat Sarmadi, S ; Sharif University of Technology
    Abstract
    The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

    Towards dark silicon era in FPGAs using complementary hard logic design

    , Article Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 ; Sept , 2014 , pp. 1 - 6 ; ISBN: 9783000446450 Ahari, A ; Khaleghi, B ; Ebrahimi, Z ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

    Emerging non-volatile memory technologies for future low power reconfigurable systems

    , Article 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC ; 26-28 May , 2014 , pp. 1-2 ; 9781479958108 Ahari, A ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    Non-volatile memory (NVM) technologies are promising alternatives to traditional CMOS memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in reconfigurable systems such as Field-Programmable Gate Arrays (FPGAs). In this paper, we investigate the applicability of different NVM technologies for the configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). Quantitative analysis for various FPGA architectures using different memory technologies shows the benefits of the proposed scheme  

    A power-efficient reconfigurable architecture using PCM configuration technology

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2014 Ahari, A ; Asadi, H ; Khaleghi, B ; Tahoori, M. B ; Sharif University of Technology
    Abstract
    Promising advantages offered by resistive NonVolatile Memories (NVMs) have brought great attention to replace existing volatile memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in Field-Programmable Gate Arrays (FPGAs). One major limitation of employing NVMs in FPGAs is significant power and area overheads imposed by the Peripheral Circuitry (PC) of NVM configuration bits. In this paper, we investigate the applicability of different NVM technologies for configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). The proposed PCM-based architecture has been... 

    Development of an embedded FPGA-based data acquisition system dedicated to zero power reactor noise experiments

    , Article Metrology and Measurement Systems ; Vol. 21, issue. 3 , Aug , 2014 , p. 433-446 ; 08608229 Arkani, M ; Khalafi, H ; Vosoughi, N ; Sharif University of Technology
    Abstract
    An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit × 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure... 

    Fault tolerant operation of single-ended non-isolated DC-DC converters under open and short-circuit switch faults

    , Article 2013 15th European Conference on Power Electronics and Applications, EPE 2013 ; 2013 ; ISBN: 9781479901166 Jamshidpour, E ; Shahbazi, M ; Poure, P ; Gholipour, E ; Saadate, S ; Sharif University of Technology
    2013
    Abstract
    Fault tolerant operation of single-ended non-isolated DC-DC converters used in embedded and safety critical applications is mandatory to guaranty service continuity. This paper proposes a new, fast and efficient FPGA-based open and short-circuit switch fault diagnosis asssociated to fault tolerant converter topology. The results of Hardware-In-the-Loop and experimental tests are presented and discussed  

    Efficient implementation of real-time ECG derived respiration system using cubic spline interpolation

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 1083-1086 ; 02714310 (ISSN) ; 9781467357609 (ISBN) Shayei, A ; Ehsani, S. P ; Shabany, M ; Sharif University of Technology
    2013
    Abstract
    Monitoring the respiratory signal is crucial in many medical applications. Traditional methods for the respiration measurement are normally based on measuring the volume of air inhaled and exhaled by lungs (like spirometer) or oxygen saturation in blood. However, these methods have numerous challenges including their high cost and not being accessible in some cases. In this paper, an algorithm for deriving the respiratory signal from ECG signal is proposed, which is based on other proposed algotithms. This algorithm uses the cubic spline interpolation (CSI) of R-waves in ECG to derive the respiratory signal. The CSI algorithm is made efficient with respect to ECG features in order to reduce... 

    Wind energy conversion system based on DFIG with open switch fault tolerant six-legs AC-DC-AC converter

    , Article Proceedings of the IEEE International Conference on Industrial Technology, Cape Town ; February , 2013 , Pages 1656-1661 ; 9781467345699 (ISBN) Shahbazi, M ; Zolghadri, M. R ; Poure, P ; Saadate, S ; The Institute of Electrical and Electronics Engineers (IEEE); IEEE Industrial Electronics Society (IES); IEEE Technology Management Council; IEEE Region 8; IEEE South Africa Section IE/IA/PEL Joint Chapter ; Sharif University of Technology
    2013
    Abstract
    Continuity of service of wind energy conversion systems as well as their reliability and performances are some of the major concerns in this power generation area. Six-legs AC/DC/AC converters are normally used in modern wind energy systems like as in the system with a doubly-fed induction generator (DFIG). A sudden failure of the converter can lead to the total or partial loss of the control of the phase currents and can cause serious system malfunction or shutdown. Therefore, to prevent the spread of the fault to the other system components and to ensure continuity of service, fault tolerant converter topologies associated to quick and effective fault detection and compensation methods... 

    Maestro: A high performance AES encryption/decryption system

    , Article Proceedings - 17th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2013 ; October , 2013 , Pages 145-148 ; 9781479905621 (ISBN) Biglari, M ; Qasemi, E ; Pourmohseni, B ; Computer Society of Iran; IPM ; Sharif University of Technology
    IEEE Computer Society  2013
    Abstract
    High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable...