Sharif Digital Repository

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable... 

In this paper, a novel neuro-fuzzy computing system is proposed where its learning is based on the creation of fuzzy relations by using a new implication method without utilizing any exact mathematical techniques. Then, a simple memristor cross-bar-based analog circuit is designed to implement this neuro-fuzzy system which offers very interesting properties. In addition to high connectivity between neurons and being fault tolerant, all synaptic weights in our proposed method are always non-negative, and there is no need to adjust them precisely. Finally, this structure is hierarchically expandable, and it can do fuzzy operations in real time since it is implemented through analog circuits.... 

A large number of Wireless Sensor Network (WSN) security schemes have been proposed in the literature, relying primarily on symmetric key cryptography. To enable those, Random Key pre-Distribution (RKD) systems have been widely accepted. However, WSN nodes are vulnerable to physical compromise. Capturing one or more nodes operating with RKD would give the adversary keys to compromise communication of other benign nodes. Thus the challenge is to enhance resilience of WSN to node capture, while maintaining the flexibility and low-cost features of RKD. We address this problem, without any special-purpose hardware, proposing a new and simple idea: key splitting. Our scheme does not increase... 

Many quantum systems are being investigated in the hope of building a large-scale quantum computer. All of these systems suffer from decoherence, resulting in errors during the execution of quantum gates. Quantum error correction enables reliable quantum computation given unreliable hardware. Unoptimized topological quantum error correction (TQEC), while still effective, performs very suboptimally, especially at low error rates. Hand optimizing the classical processing associated with a TQEC scheme for a specific system to achieve better error tolerance can be extremely laborious. We describe a tool, AUTOTUNE, capable of performing this optimization automatically, and give two highly... 

In an introductory course of computer architecture, it is of high value that students use a simple and special CPU designed for this purpose and also its graphical simulator for better understanding of the computer hardware operation. In this paper, we present Abu-Reiahn, a simple 8-bit processor which we have specifically designed and built as the introduction part of computer architecture course to help students familiarize with hardware and software of a real CPU. Effective use of our computer graphical simulator along with the hardware allow the students to deepen their knowledge of logic circuits and the need for desired timing signals in a CPU to perform specific tasks  

Support Vector Machine (SVM) is a powerful machine-learning tool for pattern recognition, decision making and classification. SVM classifiers outperform other classification technologies in many applications. In this paper, two implementations of SVM classifiers are presented using Logarithmic Number System. In the basic classifier all operations (multiplication, addition and ...) are performed using logarithmic numbers. In the logarithmic domain, multiplication and division can be simply treated as addition or subtraction respectively. The main disadvantage of LNS is the large memory requirement for high precision addition and subtraction. In the improved classifier, multiplication... 

Memristive devices have gained significant research attention lately because of their unique properties and wide application spectrum. In particular, memristor-based resistive random access memory (RRAM) offers the high density, low power, and low volatility required for next-generation nonvolatile memory. Nowadays, despite significant advances in hardware technology, in the case of massively parallel systems still new computational architectures are required. Simulation of large quantity of memristors in the crossbar structure is a known challenge encountering these barriers. Using graphic processing units (GPU) as a low-cost and high-performance computing platform is an efficient preferred... 

Theoretical and numerical analyses of rotating disks with non-uniform thickness and material properties subjected to thermo-mechanical loadings have been carried out by variable material properties (VMP), Runge-Kutta's (RK) and finite element (FE) methods. The material is assumed to be elastic-linear hardening. A power form function is used to describe the temperature gradient with the higher temperature at outer surface. Von-Mises theory has been used as failure criterion. The effects of geometry, material and thermal loading parameters as well as boundary conditions on radial, hoop and equivalent stress distributions which have not been studied in much detail in previous works have been... 

Multiple paths are mainly used in order to achieve higher throughput and reduce the end-to-end delivery latency as well. However, the overall network performance greatly suffers from the available interference between paths, even if node disjoint multipaths are used. This problem is highlighted more when dealing with transmission of the video data where the timeliness is of primary concern. In this paper, we propose a novel Interference-Aware Multipath routing for Video Delivery (IAMVD) in the realm of wireless multimedia sensor networks. It constructs multiple paths while considering the effect of different QoS requirements of multi-priority packets, without needing any hardware support for... 

In this paper we have proposed an efficient method based on Genetic Algorithms (GAs) to design quantum cellular automata (QCA) circuits with minimum possible number of gates. The basic gates used to design these circuits are 2-input and 3-input NAND gates in addition to inverter gate. Due to use of these two types of NAND gates and their contradictory effects, a new fitness function has been defined. In addition, in this method we have used a type of mutation operator that can significantly help the GA to avoid local optima. The results show that the proposed approach is very efficient in deriving NAND based QCA designs  

There has been a strong push recently to examine biological scale simulations of neuromorphic algorithms to achieve stronger inference capabilities. This paper presents a set of piecewise linear spiking neuron models, which can reproduce different behaviors, similar to the biological neuron, both for a single neuron as well as a network of neurons. The proposed models are investigated, in terms of digital implementation feasibility and costs, targeting large scale hardware implementation. Hardware synthesis and physical implementations on FPGA show that the proposed models can produce precise neural behaviors with higher performance and considerably lower implementation costs compared with... 

Electrical Impedance Tomography (EIT), is one of the medical imaging technologies. It can also be used in industrial process monitoring. In this method, the image of the electrical conductivity distribution of the inner part of a conductive subject can be reconstructed. The image reconstruction process is done by injecting an accurate current into the boundary of a conductive subject (e.g. body), measuring the voltages around the boundary and transmitting them to a computer, and processing on acquired data with a software (e.g., MATLAB). The images are obtained from the peripheral data by using an algorithm. Precise EIT instrumentation plays an important role in the final images quality. In... 

This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The... 

This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions and generate signatures for the running program, and 2) an external watchdog processor to compare runtime signatures and branch addresses with the information extracted offline. The proposed method is implemented on an embedded processor core and is evaluated by a simulation based statistical fault injection approach where faults are injected into cache and main memory. Experimental results show that the proposed method detects more than... 

Programmable hardware is gaining popularity as it can keep pace with growing performance demand in tight power budget, design and test cost, and serious reliability concerns of future multiprocessor embedded systems. Compatible with this trend, Network-on-Chip, as a potential bottleneck of future multi-cores, should also support pro-grammability. Here, we address this issue in design and implementation of routing algorithm for two-dimensional mesh. To this end, we allocate paths based on input traffic pattern and in parallel with customizing routing restriction for deadlock freedom. To achieve this, we propose extended turn model (ETM), a novel parametric deadlock-free routing for 2D meshes... 

This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

Ink drop spread (IDS) is the engine of an active learning method, which is the methodology of soft computing. IDS, as a pattern-based processing unit, extracts useful information from a system that is subjected to modeling. In spite of its excellent potential to solve problems such as classification and modeling compared with other soft-computing tools, finding its simple and fast hardware implementation is still a challenge. This paper describes a new hardware implementation of the IDS method that is based on the memristor crossbar structure. In addition to simplicity, being completely real time, having low latency, and the ability to continue working properly after the occurrence of power... 

FPGAs are interesting choices for control of power electronics converters and electrical drives. In this paper, implementation of the control method of a reduced switch- count five-leg converter is carried out. Two PWM methods are studied. For verification of the implemented controller in a practical manner, without risking the damaging of the real system, "FPGA in the loop" experiments are performed. It is shown that using the proposed methodology, FPGA implementation and verification is fast and effective. The provided results show the high performance of the implemented controller on the FPGA, therefore the feasibility and suitability of the FPGA for this application is approved  

Multiple Description Coding (MDC) is a technique where multiple streams from a source are generated, each individually decodable and mutually refinable. In this paper, a new Mixed Layer MDC (MLMDC) scheme is presented which achieves a higher side quality compared to conventional MDCs. The improved side performance leads to higher average video quality at the receiver in lossy networks. For each DCT coefficient, we generate two coefficients: Base Coefficient (BC) and Enhancement Coefficient (EC) which are combined together. When all descriptions are available, they are decomposed and decoded to achieve high quality video. When one description is not available, we use estimation to extract as... 

In this paper we have presented a hardware implementation of 32-bit Fault-tolerant ALU (Arithmetic and Logic Unit) which is compared with the current techniques, Residue code, Triple Modular Redundancy (TMR) with single voting and TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA (Field Programmable Gate Array). The new implementation of ALU employing BCH code on Spartan-3 FPGA has been provided. The results show that our fault tolerant method has the lowest hardware overhead and it can correct any 5-bit error in any...