Sharif Digital Repository

Integrated silicon photonic networks have attracted a lot of attention in the recent decades due to their potentials for low-power and high-bandwidth communications. However, these promising networks, as the future technology, are drastically susceptible to thermal fluctuations, which may paralyze wavelength-based operation of these networks. In this regard, precise addressing of thermally induced faults in optical networks-on-chip (ONoCs), as well as revealing practical methods to tackle this challenge will be a break-even point toward implementation of this technology. In this paper, thermal variation is investigated through analyzing on-chip power distribution, which is addressed by power... 

Triple Modular Redundancy (TMR) is a historical and long-time-used approach for masking various kinds of faults. By employing redundancy and analyzing the results of three separate executions of the same program, TMR is able to attain excellent levels of reliability. While TMR provides a desirable level of reliability, it suffers from the high power consumption of the redundant hardware, a severe detriment to its broad adoption. The energy consumption of TMR can be mitigated if its operations are divided into two stages, and one stage is dropped in the absence of fault. Such an approach, which is evaluated in recent research, however, quickly fails in the presence of permanent faults, as we... 

Triple Modular Redundancy (TMR) is a historical and long-time-used approach for masking various kinds of faults. By employing redundancy and analyzing the results of three separate executions of the same program, TMR is able to attain excellent levels of reliability. While TMR provides a desirable level of reliability, it suffers from the high power consumption of the redundant hardware, a severe detriment to its broad adoption. The energy consumption of TMR can be mitigated if its operations are divided into two stages, and one stage is dropped in the absence of fault. Such an approach, which is evaluated in recent research, however, quickly fails in the presence of permanent faults, as we... 

Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core... 

A high-precision delay chain circuit integrated in a 0.18- mu ext{m} CMOS technology working in the frequency bandwidth of 8-18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay... 

Sensors are among essential building blocks of any Cyber-Physical Systems (CPSs). Acquisition and processing of their sensory data contribute to the power consumption and computation load of the overall CPSs. For data acquisition, the conventional fixed frequency sampling in many such systems is sub-optimal since a sizable number of samples do not contain important information. In this work, we propose a Signal-Dependent Sampling (SDS) method and present its associated circuit implementation. Using the proposed SDS method, the number of retained samples is significantly reduced with little or negligible compromise in the quality of the (reconstructed) signal. The associated error and added... 

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are... 

The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks especially against differential power analysis attacks. Our approach is a modified version of a classical charge recovery logic style namely 2N-2N2P. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with 2N-2N2P and other DPA-resistant logic styles. Copyright 2008 ACM  

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during a read/write operation, only selected cell is connected to bit-line when one row is selected whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. Proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS... 

A new low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.18um CMOS technology, with a power supply of 1.4 volt. The results show PSRR is 65dB at 1MHz and the output voltage variation versus temperature (-40 to 140) is less than 0.1%. This circuit shows robustness against process variation. ©2008 IEEE  

A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power... 

Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the most important concerns in NoC architecture design. The choice of network topology is important in designing a low-power and high-performance NoC. In this paper, we propose the use of the WK-recursive networks to be used as the underlying topology in NoC. We have implemented VHDL hardware model of mesh and WK-recursive topologies and measured the latency results using simulation with these implementation. We also propose a novel approach in high level power modeling based on latency for these topologies and show that... 

This paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded-cascode amplifier (FCA) results in 7× slew rate... 

Internet traffic recognition is essential for access providers since it helps them define adapted priorities in order to enhance user experience, e.g., a high priority for an audio conference and a low priority for a file transfer. As internet traffic becomes increasingly encrypted, the main classic traffic recognition technique, payload inspection, is rendered ineffective. Hence this paper uses machine learning techniques looking only at packet size and time of arrival. For the first time, Spiking neural networks (SNNs), which are inspired by biological neurons, were used for this task for two reasons. Firstly, they can recognize time-related data packet features. Secondly, they can be... 

This paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded-cascode amplifier (FCA) results in 7× slew rate... 

This paper adopts a holistic approach to stress detection issues in software and hardware phases and aims to develop and evaluate a specific low-power and low-cost sensor using physiological signals. First, a stress detection model is presented using a public data set, where four types of signals, temperature, respiration, electrocardiogram (ECG), and electrodermal activity (EDA), are processed to extract 65 features. Using Kruskal-Wallis analysis, it is shown that 43 out of 65 features demonstrate a significant difference between stress and relaxed states. K nearest neighbor (KNN) algorithm is implemented to distinguish these states, which yields a classification accuracy of 96.0 ± 2.4%. It... 

Optical Neural Networks (ONNs) can be promising alternatives for conventional electrical neural networks as they offer ultra-fast data processing with low energy consumption. However, lack of suitable nonlinearity is standing in their road of achieving this goal. While this problem can be circumvented in feed-forward neural networks, the performance of the recurrent neural networks (RNNs) depends heavily on their nonlinearity. In this paper, we first propose and numerically demonstrate a novel reconfigurable optical activation function, named ROA, based on adding or subtracting the outputs of two saturable absorbers (SAs). RAO can provide both bounded and unbounded outputs by facilitating an... 

This article reports the development of a new smart electrocardiogram (ECG) monitoring system, consisting of the related hardware, firmware, and Internet of Things (IoT)-based web service for artificial intelligence (AI)-assisted arrhythmia detection and a complementary Android application for data streaming. The hardware aspect of this article proposes an ultralow power patch sampling ECG data at 256 samples/s with 16-bit resolution. The battery life of the device is two weeks per charging, which alongside the flexible and slim (193.7 mm times62.4 mm times8.6 mm) and lightweight (43 g) allows the user to continue real-life activities while the real-time monitoring is being done without... 

Boost converter operating in critical conduction mode is widely used in low-power power factor corrector because of its simplicity and low switching losses. The switching loss due to parasitic capacitor discharge at the on-time instant can also be reduced by a valley switching technique. In this paper, we introduce a new driver topology for the high-side switch in a synchronous boost converter operating in the critical conduction mode to obtain full zero-voltage switching. Using the proposed high-side driver topology, the conventional control circuit is sufficient to control the low-side switch, and no additional control circuit is required to adjust the timing of the switches. Finally, the...