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A Low-power clock generator with a wide frequency tuning range and low temperature variation: analysis and design
, Article Journal of Circuits, Systems and Computers ; Volume 29, Issue 1 , 2020 ; Shokrekhodaei, M ; Atarodi, M ; Sharif University of Technology
World Scientific Publishing Co. Pte Ltd
2020
Abstract
This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit...
, M.Sc. Thesis Sharif University of Technology ; Jahed, Mehran (Supervisor) ; Miremadi, Ghasem (Supervisor)
Abstract
Considering ever expanding applications of embedded systems in all aspects of human life, reliability and fault tolerance of these systems have become vital. To increase the reliability in a microprocessor as the most critical component of an embedded system, one may notice the essential role that is offered by its register bank. In fact the register bank is the most critical subcomponent of an embedded system, greatly affecting the reliability of the overall system. The operation of the embedded system is further critically affected through optimal and efficient usage of power as most systems relay on battery. In this project, to evaluate the availability of register banks various...
Value-Aware low-power register file architecture
, Article CADS 2012 - 16th CSI International Symposium on Computer Architecture and Digital Systems ; 2012 , Pages 44-49 ; 9781467314824 (ISBN) ; Fazeli, M ; Ghalaty, N. F ; Miremadi, S. G ; Sharif University of Technology
2012
Abstract
In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure
Zero-power mismatch-independent Digital to Analog converter
, Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): - 4 ; 9781479988938 (ISBN) ; Sendi, M. S. E ; Nikoofard, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply
Low-power technique for dynamic comparators
, Article Electronics Letters ; Volume 52, Issue 7 , 2016 , Pages 509-511 ; 00135194 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Institution of Engineering and Technology
Abstract
A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-ampli-fication phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%
An 8-bit 160 MS/s folding-interpolating adc with optimizied active averaging/interpolating network
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 6150-6153 ; 02714310 (ISSN) ; Movahedian, H ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE
A new full CMOS 2.5-V two-stage line driver with variable gain for ADSL applications
, Article 2004 IEEE International Symposium on Circuits and Systems - Proceedings, Vancouver, BC, 23 May 2004 through 26 May 2004 ; Volume 4 , 2004 , Pages IV-405-IV-408 ; 02714310 (ISSN) ; Atarodi, M ; Aslanzadeh, H. A ; Saeedi, S ; Safarian, A. Q ; Sharif University of Technology
2004
Abstract
In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology
An efficient fast switching procedure for stepwise capacitor chargers
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume PP, Issue 99 , 2016 ; 10638210 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching...
MFLP: a low power encoding for on chip networks
, Article Design Automation for Embedded Systems ; Volume 20, Issue 3 , 2016 , Pages 191-210 ; 09295585 (ISSN) ; Taassori, M ; Uysal, S ; Sharif University of Technology
Springer New York LLC
2016
Abstract
Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approach assigns the symbols to data word in such a way that the more frequent words are sent by less power consumption. This algorithm dedicates the symbols with less ones to high probability data and uses transition signaling to transmit data. The proposed method, unlike the existing low power encoding, does not rely on spatial redundancy and keeps the...
Effects of RPL objective functions on the primitive characteristics of mobile and static IoT infrastructures
, Article Microprocessors and Microsystems ; Volume 69 , 2019 , Pages 79-91 ; 01419331 (ISSN) ; Mohammad Salehi, A. A ; Hosseini Monazzah, A. M ; Ejlali, A ; Sharif University of Technology
Elsevier B.V
2019
Abstract
The emergence of mobile IoT applications in recent years and the challenge of routing in their infrastructures have motivated scholars to propose appropriate routing mechanisms for such systems. Meanwhile, the IPv6 Routing Protocol for Low Power and Lossy Networks (RPL) is the standard routing protocol for IoT infrastructures. Nevertheless, RPL was mainly designed to comply with the primitive requirements of static IoT applications and it behaves poorly in confronting with the severe alterations in mobile conditions. The most important factor for such a poor behavior in mobile applications is the inappropriate design of OFs, which determine RPL's routing policies in the network. Therefore,...
Self-Powered soil moisture monitoring sensor using a picoampere quiescent current wake-up circuit
, Article IEEE Transactions on Instrumentation and Measurement ; Volume 69, Issue 9 , 2020 , Pages 6613-6620 ; Habibi, M ; Magierowski, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2020
Abstract
Low-power wireless stand-alone sensors that can operate without any wiring have received significant attention in sensor network applications. These devices harvest environmental energy resources to supply their power and transfer their collected data using wireless RF links. In many instances, the power supplied from the environment is far less than the power required by the sensor device. In this case, the main solution is to accumulate energy on a storage element, and when enough energy is stored, the sensor node is instantaneously activated using an undervoltage lockout (UVLO) circuit. During this short time burst, the sensor performs the required acquisition, transmits the results, and...
ARMOR: A reliable and mobility-aware RPL for mobile internet of things infrastructures
, Article IEEE Internet of Things Journal ; Volume 9, Issue 2 , 2022 , Pages 1503-1516 ; 23274662 (ISSN) ; Safaei, B ; Monazzah, A. M. H ; Bauer, L ; Henkel, J ; Ejlali, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2022
Abstract
Mobile portable embedded devices are becoming an integral part of our daily activities in the vision of Internet of Things (IoT). Nevertheless, due to lack of mobility support in the IPv6 routing protocol for low-power and lossy networks (RPLs), which is standardized for multihop IoT infrastructures, providing reliable communications in terms of packet delivery ratio (PDR) in mobile IoT applications has become significantly challenging. While several studies tried to enhance the adaptability of RPL to network dynamics, their utilized routing metrics have prevented them from establishing long-lasting reliable paths. Furthermore, the stochastic parent replacement policy in the standard version...
Design of an UWB Analogue Detector Receiver for Biomedical Applications
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor) ; Fotowat-Ahmady, Ali (Co-Advisor)
Abstract
Emergence of the implantable biomedical microsystems and personal area networks in recent years result in a new class of biomedical systems that requires data transmition in short range at various data rates. Performing with ultra low power consumption and long battery life are crucial in these systems. Therefore, designing low power radios for these systems is still an active research area. Ultera wideband systems are specially considered for implementations because of their potential characteristics.
In this dissertation, different biomedical applications and data communication approaches are surveyed. Then, Different architectures of UWB receivers are reviewed. To implement a low...
In this dissertation, different biomedical applications and data communication approaches are surveyed. Then, Different architectures of UWB receivers are reviewed. To implement a low...
High-Speed Low-Power 10-bit Pipeline Analog to Digital Converter
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor) ; Atarodi, Mojtaba (Supervisor)
Abstract
High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 40 M sample/s with a power consumption of 20mW for the input level of 1Vp-p and a 1V power supply in 0.13μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized analytically which leads to simple back-envelope formulas to...
Systematic Design of Low Power Flash ADC
, Ph.D. Dissertation Sharif University of Technology ; Sadughi, Sirus (Supervisor) ; Sharifkhani, Mohamad (Co-Advisor) ; Atarodi, Mojtaba (Co-Advisor)
Abstract
Considering the drastical increasing of greenhouse gases in the atmosphere, especially carbon dioxide, reduction of these gases seems necessary to combat global warming. Fossil fuel power plants are one of the main sources of CO2 emission. In this thesis, CO2 capture from a natural gas fired combined cycle power plant using different oxygen percent in air feed is studied. Aspen Plus was used to evaluate the effect of this capture technology on the plant efficiency and energetic parameters of the system. Aspen Hysys is used to simulate Amine absorption tower and Air Separation cryogenic tower. Since the oxygen production plant, CO2 capture and transport are cost and energy intensive, the cost...
Low-Power Reconfigurable Pipeline ADC for Multi-Standard Communication
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor) ; Shoaee, Omid (Co-Advisor)
Abstract
With the rapid development of wireless communication standards, the co-existence of multiple standards in a single chip becomes inevitable. It is also fueling interest in analog to digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions with adaptive power consumption. Employing such ADCs rather than using multiple individually power-optimized ADCs results in a great reduction of silicon area. Hence, a reconfigurable ADC can reduce time to market, and save costs.
This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The...
This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The...
Design and Implementation of Low Power Delta Sigma Modulator for Audio Application
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
iN This thesis, Design and implementation of a low voltage, low power Delta-Sigma Modulator (DSM) is presented. System level considerations have been discussed thoroughly. In addition a systematic design flow in the context of continuous time delta sigma modulators is provided. While voltage-domain signal processing becomes more difficult in deep sub-micron processes, a finer time resolution is achievable. Time-domain quantizers can ameliorate the design challenges of flash quantizers which arises from lower supply voltages and higher fraction of comparator metastable region. VCO based quantizer such as voltage to frequency and voltage to phase considered as time domain quantizers can be a...
Effect of Low Power CW Laser (He-Ne)on Artemia Cyst
, M.Sc. Thesis Sharif University of Technology ; Sadighi Bonabi, Rasoul (Supervisor)
Abstract
Artemia (brine shrimp) is a genus of crustaceans that lives in saltwater and due to having unique features, in producing the food and nutrients needed for larvae and other types of farmed sea creatures, is of great importance. In its natural environment under certain conditions, Artemia produces cysts that float at the water surface and are driven ashore by wind and waves. These cysts are inactive and do not develop further as long as they are kept dry. Upon immersion in seawater, the biconcave cysts hydrate and become spherical and, within the shell, the embryo resumes its interrupted metabolism. After about 20 h the outer membrane of the cyst breaking and the embryo appears, surrounded by...
Design of Ultra Low Power RF Front-End Based on Current Reuse for Bluetooth Low Energy Standard
, M.Sc. Thesis Sharif University of Technology ; Safarian, Aminghasem (Supervisor) ; Atarodi, Mojtaba (Co-Supervisor)
Abstract
Bluetooth low energy, originally developed by Nokia as wibree, was formally introduced by SIG group in 2010. It is a promising technology for internet of things (IoT) which needs ultra low power consumption. Unlike digital circuits that the power consumption decreases with technology scaling and consequently decreasing the supply voltage, the scaling has not such effect in analog circuits for two reasons. First, the power consumption of an analog circuit is mainly determined by its noise and linearity specification which in almost all cases is determined by the standard. Second, due to noise consideration, analog designers prefer to not to use the latest technology for example because of...
Selective Wake-Up Receiver for Dense Environment
, M.Sc. Thesis Sharif University of Technology ; Sharif Bakhtiar, Mehrdad (Supervisor)
Abstract
An ultra-low-power wake-up receiver is proposed, which reduces the power consumption significantly under the two-mode duty-cycling and with negligible latency. Due to the use of an accurate LO and high Q BB filters, the receiver shows a perfect selectivity in the frequency domain, and appropriately fits practical dense environment applications. In this receiver, four start frame bits (SFB) are received at the low data rate of 1 kbps in the MO mode, and after entering the ID mode, a long wake-up pattern is received at the high data rate of 100 kbps. Therefore, the latency is limited to the SFBs and is roughly 4 msec. The proposed wake-up receiver is designed and fabricated in TSMC 180 nm...