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Two-dimensional multi-parameter adaptation of noise, linearity, and power consumption in wireless receivers
, Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, issue. 8 , July , 2014 , p. 2433-2443 ; Sharif Bakhtiar, M ; Sharif University of Technology
Abstract
This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,...
12 bits, 40MS/s, low power pipelined SAR ADC
, Article Midwest Symposium on Circuits and Systems ; Aug , 2014 , p. 841-844 ; Hajsadeghi, K ; Sharif University of Technology
Abstract
This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method
Dynamically adaptive register file architecture for energy reduction in embedded processors
, Article Microprocessors and Microsystems ; Volume 39, Issue 2 , March , 2015 , Pages 49-63 ; 01419331 (ISSN) ; Ahmadian Khameneh, S ; Goudarzi, M ; Sharif University of Technology
Elsevier
2015
Abstract
Energy reduction in embedded processors is a must since most embedded systems run on batteries and processor energy reduction helps increase usage time before needing a recharge. Register files are among the most power consuming parts of a processor core. Register file power consumption mainly depends on its size (height as well as width), especially in newer technologies where leakage power is increasing. We provide a register file architecture that, depending on the application behavior, dynamically (i) adapts the width of individual registers, and (ii) puts partitions of temporarily unused registers into low-power mode, so as to save both static and dynamic power. We show that our scheme...
Low-power bottom-plate sampling capacitor-splitting DAC for SAR ADCs
, Article Electronics Letters ; Volume 52, Issue 11 , 2016 , Pages 913-915 ; 00135194 (ISSN) ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
Institution of Engineering and Technology
2016
Abstract
A highly energy-efficient switching method for capacitor-splitting digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. In the proposed DAC, a bottom-plate sampling method is introduced which requires only one reference voltage (Vcm = 1/2Vref) during the entire DAC switching steps. Therefore, in addition to the switching energy reduction, the precision of the DAC is increased since only one reference voltage is used. The DAC average switching energy and the area are reduced by 98.44% and 50% compared with the conventional binary weighted DAC
A low power high resolution time to digital converter for ADPLL application
, Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and...
Design of low power comparator-reduced hybrid ADC
, Article Microelectronics Journal ; Volume 79 , 2018 , Pages 79-90 ; 00262692 (ISSN) ; Hajsadeghi, K ; Khorami, A ; Sharif University of Technology
Elsevier Ltd
2018
Abstract
This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s...
SPONGE: a scalable pivot-based on/off gating engine for reducing static power in NoC routers
, Article Proceedings of the International Symposium on Low Power Electronics and Design23 July 2018 ; 23-25 July , 2018 ; 15334678 (ISSN) ; 9781450357043 (ISBN) ; Mardani Kamali, H ; Jerger, N. E ; Hessabi, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
Due to high aggregate idle time of Networks-on-Chip (NoCs) routers in practical applications, power-gating techniques have been proposed to combat the ever-increasing ratio of static power. Nevertheless, the sporadic packet arrivals compromise the effectiveness of power-gating by incurring significant latency and energy overhead. In this paper, we propose a Scalable Pivot-based On/Off Gating Engine (SPONGE) which efficiently manages power-gating decisions and routing mechanism by adaptively selecting a small set of powered-on columns of routers and keeping the others in power-gated state. To this end, a router architecture augmented with a novel routing algorithm is proposed in which a...
A low-power comparator-reduced flash ADC using dynamic comparators
, Article 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, 5 December 2017 through 8 December 2017 ; Volume 2018-January , 2018 , Pages 5-8 ; 9781538619117 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE
Lazy instruction scheduling: Keeping performance, reducing power
, Article ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, 11 August 2008 through 13 August 2008 ; 2008 , Pages 375-380 ; 15334678 (ISSN); 9781605581095 (ISBN) ; Taghizadeh, M ; Jahangir, A. H ; Sharif University of Technology
2008
Abstract
An important approach to reduce power dissipation is reducing the number of instructions executed by the processor. To achieve this goal, this paper introduces a novel instruction scheduling algorithm that executes an instruction only when its result is required by another instruction. In this manner, it not only does not execute useless instructions, but also reduces the number of instructions executed after a mispredicted branch. The cost of the extra hardware is 161 bytes for 128 instruction window size. Measurements done using SPEC CPU 2000 benchmarks show that the average number of executed instructions is reduced by 13.5% while the average IPC is not affected. Copyright 2008 ACM
A two-stage pipelined passive charge-sharing SAR ADC
, Article APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; January , 2008 , Pages 141-144 ; 9781424423422 (ISBN) ; Bakhtiar, M. S ; Sharif University of Technology
2008
Abstract
This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18um CMOS process, the 12-bits, 40MS/sec ADC core consumes 7mW from a 1.8V supply
A low-power, second-order Δ/∑ modulator using a single class-AB op-amp for voice-band applications
, Article Analog Integrated Circuits and Signal Processing ; Volume 49, Issue 2 , 2006 , Pages 199-211 ; 09251030 (ISSN) ; Sahandiesfanjani, F ; Heydari, P ; Atarodi, S. M ; Sharif University of Technology
2006
Abstract
The design of a power-efficient second-order Δ/∑ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. © Springer Science + Business Media, LLC 2006
An analytic approach used to design a low power and low phase noise CMOS LC oscillator
, Article 2004 IEEE International Frequency Control Symposium and Exposition. A Conference of the IEEE Ultrasonics, Ferroelectrics, and Frequency Control Society (UFFC-S), Montreal, 23 August 2004 through 27 August 2004 ; 2005 , Pages 432-435 ; Behroozi, H ; Yuhas M.P ; Sharif University of Technology
2005
Abstract
An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS LC oscillator is discussed. The phase noise performance for this kind of oscillator is predicted by using a simplified model. This method enables us to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the presented method is demonstrated by designing an LC CMOS oscillator in a 0.24μm CMOS technology. The predictions obtained from the derived expressions are in good agreement with simulation results over a wide range of the supply voltage. © 2004 IEEE
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "slew boost" technique
, Article Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03), Seoul, 25 August 2003 through 27 August 2003 ; 2003 , Pages 340-344 ; 15334678 (ISSN) ; Mehrmanesh, S ; Vahidfar, M. B ; Safarian, A. Q ; Lotfi, R ; Sharif University of Technology
Association for Computing Machinery
2003
Abstract
An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called "Slew Boost" is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10bit 150MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp using 0.18um CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than 1mW from a single supply of 1 volt
Recycling forward and backward frequency-multiplexed modes in a waveguide coupled to phased time-perturbed microrings for low-footprint neuromorphic computing
, Article Optical Materials Express ; Volume 12, Issue 3 , 2022 , Pages 1198-1213 ; 21593930 (ISSN) ; Memarian, M ; Mehrany, K ; Sharif University of Technology
The Optical Society
2022
Abstract
Optical structures can serve as low-power high-capacity alternatives of electronic processors for more efficient neuromorphic computing, but can suffer from large footprints and weak scalability. In this work, properly phased time-perturbed microrings side-coupled to a waveguide are utilized to realize a compact processor for linear transformations. We build up a synthetic frequency dimension to provide sufficient degrees of freedom, where the linear time-varying structures enable the linear intermixing and transformation of frequency-multiplexed data. Moreover, non-reciprocal and asymmetric flow of data in the forward and backward modes, due to phasing of the perturbations, helped to build...
Efficient Circuit and Systematic Design of Successive Approximation Register Analog to Digital Converters
, Ph.D. Dissertation Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to...
All-optical wavelength-routed architecture for a power-efficient network on chip
, Article IEEE Transactions on Computers ; Vol. 63, issue. 3 , 2014 , p. 777-792 ; Hessabi, S ; Sharif University of Technology
Abstract
In this paper, we propose a new architecture for nanophotonic Networks on Chip (NoC), named 2D-HERT, which consists of optical data and control planes. The proposed data plane is built upon a new topology and all-optical switches that passively route optical data streams based on their wavelengths. Utilizing wavelength routing method, the proposed deterministic routing algorithm, and Wavelength Division Multiplexing (WDM) technique, the proposed data plane eliminates the need for optical resource reservation at the intermediate nodes. For resolving end-point contention, we propose an all-optical request-grant arbitration architecture which reduces optical losses compared to the alternative...
Development of a non-invasive micron sized blood glucose sensor based on microsphere stimulated raman spectroscopy
, Article Sensors and Transducers ; Volume 147, Issue 12 , 2012 , Pages 129-142 ; 17265479 (ISSN) ; Jahangiri, N ; Taraz, M ; Sharif University of Technology
2012
Abstract
We proposed a new method for Non-invasive measuring of blood glucose levels by using micro sphere Stimulated Raman scattering. We show that this method can be used to measure biological glucose levels with low power lasers. The field enhancement due to the resonance condition of high quality factor microsphere causes to reduce stimulated Raman scattering thresholds of its surrounding media (glucose) and hence observing stimulated Raman scattering with low power. The results from theoretical studies indicate that the stimulated Raman signal amplitude levels produced from the very low Glucose concentrations. By measuring the changes of the signal intensity in output of fiber, we can determine...
A low power, eight-phase LC-ring oscillator for clock and data recovery application
, Article 2012 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, INMMIC 2012 ; 2012 ; 9781467329491 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
2012
Abstract
A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center...
A low power 1-V 10-bit 40-MS/s pipeline ADC
, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 212-215 ; 9781457718458 (ISBN) ; Sharifkhani, M ; Gholami, M ; Sharif University of Technology
2011
Abstract
A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC...
Low energy yet reliable data communication scheme for network-on-chip
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 34, Issue 12 , 2015 , Pages 1892-1904 ; 02780070 (ISSN) ; Palesi, M ; Eskandari, S ; Hessabi, S ; Afzali-Kusha, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
In this paper, a low energy yet reliable communication scheme for network-on-chip is suggested. To reduce the communication energy consumption, we invoke low-swing signals for transmitting data, as well as data encoding techniques, for minimizing both self and coupling switching capacitance activity factors. To maintain the communication reliability of communication at low-voltage swing, an error control coding (ECC) technique is exploited. The decision about end-To-end or hop-To-hop ECC schemes and the proper number of detectable errors are determined through high-level mathematical analysis on the energy and reliability characteristics of the techniques. Based on the analysis, the extended...