Sharif Digital Repository

High reliability and low power consumption are among the major requirements in design of wireless sensor networks (WSNs). In this paper, a multi-objective problem is formulated as a Joint Power consumption and data Reliability (JPR) optimization problem. For this purpose, a connected dominating set (CDS)-based topology control approach is proposed. Our objective is to self-organize the network with minimum interference and power consumption. We consider the power changes into a topology with minimum CDS infrastructure subject to connectivity constraints. Since this problem is NP-hard, it cannot be dealt with using polynomial-time exact algorithms. Therefore, we first present a genetic... 

High reliability and low power consumption are the critical objectives in wireless networks and the network topology is an effective issue in these objectives. This paper investigates these two objectives in the wireless multi-hop networks simultaneously. For this purpose, a connected dominating set CDS-based topology control approach is proposed. In this approach a distributed topology control algorithm with different power adjustment measures is suggested. Our goal is to self-organize this network with minimum interference and power consumption subject to connectivity preservation. Unlike many reliability enhancement algorithms, the proposed mechanism does not compromise power consumption.... 

In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that... 

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy... 

Scaling of CMOS devices being aggressively decreasing by reduce of transistor dimensions. However, such level of integration leads to many physical limit and transistors cannot get much smaller than their current size. Quantum-dot Cellular Automate is a novel technology which significantly reduces physical limit of CMOS devices implementation, thus, it can be an appropriate candidate to be substituted for CMOS technology. In addition to high integration density of QCA circuits, other unique specifications such as high speed and low power consumption encourage researchers to utilize this technology instead of CMOS technology. In this paper, a new layout of XOR gate is presented in QCA... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

Coupling capacitances between adjacent wires in on-chip interconnects significantly affect the amount of power consumption in Ultra-Deep-Submicron technologies. On the other hand, the propagation delay across global on chip interconnects has increasingly become a limiting factor in high-speed design. Crosstalk between adjacent links on the bus contributes a significant portion of this delay. Crosstalk noise also affects the integrity of signals. Decreasing the coupling transitions can improve the side effects of crosstalk noise. We propose an algorithm to minimize the coupling activity transition. We also introduce a new solution to fit the proposed algorithm for Network-on-Chip (NoC)... 

Simulation of large-scale nonlinear dynamical systems on hardware with a high resemblance to their mathematical equivalents has been always a challenge in engineering. This paper presents a novel current-input current-output circuit supporting a systematic synthesis procedure of log-domain circuits capable of computing bilateral dynamical systems with considerably low power consumption and acceptable precision. Here, the application of the method is demonstrated by synthesizing four different case studies: 1) a relatively complex 2-D nonlinear neuron model; 2) a chaotic 3-D nonlinear dynamical system Lorenz attractor having arbitrary solutions for certain parameters; 3) a 2-D nonlinear Hopf... 

A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-Amplifier stage) is limited to V dd=2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above V dd=2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster... 

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

A low-power technique for high-resolution comparators is introduced. In this technique, p-type metal-oxide-semiconductor field-effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter-based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n-channel metal-oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power... 

The Internet of Things (IoT) presents a new paradigm of the future Internet that intends to provide interactive communication between various processing objects via heterogeneous networks. The IPv6 over Low power Wireless Personal Area Networks (6LoWPAN) is an IPv6 adaptation sub-layer and provides the requirements of IP connectivity between resource-constrained devices in lossy, low power networks. Since the size of a packet in the IPv6 is larger than the size of a frame in the IEEE 802.15.4, the 6LoWPAN adaptation layer performs packet fragmentation. In this paper, first, the 6LoWPAN fragmentation mechanism in terms of security issues is analyzed and then, fragment duplication attack which... 

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations.... 

This paper presents a circuit level soft error-tolerant-technique, called RRC (Robust Register Caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in... 

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell,... 

A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology. © 2009 IEEE  

In this paper, a low power receiver for medical implant communication service (MICS) is presented. Low power design is vital in the MICS applications since the implanted chip has to work for a long time without the need to change its battery. As a result, a merged N-path low noise amplifier (LNA) and mixer block is proposed. In this structure, the LNA and down-conversion mixer share a transconductance to lower the overall power consumption. An N-path feedback is utilized around the shared transconductance not only to improve the LNA selectivity and relax the linearity requirements but also to downconvert the radio frequency (RF) component and create the intermediate frequency (IF) signal. In...