Sharif Digital Repository

Most modern multi-core edge devices work in outdoor situations with limited power supplies like energy harvester and batteries. Therefore, energy consumption is a fundamental issue in which the memory subsystem has a significant role. Scratchpad memories (SPM) can provide a broad potential for energy saving. Still, due to the insufficient SPM capacity in such edge devices, a rigorous SPM data allocation scheme is necessary to reduce the energy consumption of the memory subsystem. Emerging non-volatile memories (NVMs) are very useful to reduce the energy consumption of the memory subsystem. Therefore, embedded and edge devices can take advantage of hybrid SPM composed of both NVM and SRAM to... 

In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: They support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of... 

In recent years, increased I/O demand of Virtual Machines (VMs) in large-scale data centers and cloud computing has encouraged system architects to design high-performance storage systems. One common approach to improving performance is to employ fast storage devices such as Solid-State Drives (SSDs) as an I/O caching layer for slower storage devices. SSDs provide high performance, especially on random requests, but they also have limited endurance: They support only a limited number of write operations and can therefore wear out relatively fast due to write operations. In addition to the write requests generated by the applications, each read miss in the SSD cache is served at the cost of... 

Reservoir computing is a machine learning approach that enables us to use recurrent neural networks without involving the complexity of training algorithms and make hardware implementation possible. We present a novel photonic architecture of a reservoir computer that employs a nonlinear node and a resonator to implement a virtual recurrent neural network. This resonator behaves as an echo generator component that substitutes the delay line in delaybased reservoir computers available in the literature. The virtual neural network formed in our implementation is fundamentally different from the delay-based reservoir computers. Different virtual architectures based on the FSR and the Finesse of... 

This work presents a case for general support for processing-in-memory (PIM) in compilers and puts forth an approach to face it along with a simple model. The ultimate goal of the work is to implement the features in a general-purpose compiler that can compile for any homogeneous ISA system, so the benefits from PIM are not limited to niche use-cases. © 2013 IEEE  

Proper modeling of the human arm dynamic, as it interacts with telemanipulation and haptic systems, is important in enhancing the transparency of these systems. In this article, we introduced an adaptive identifier to estimate the impedance characteristic of a human operator as it interacts with a single translational degree of freedom mechanism. The five parameter model, including an extra spring and damper for a better approximation of the dynamic behavior of human arm, has been used. Since the impedance characteristic of human arm differs from one individual to another, it is important to estimate these parameters for each individual and update the controller to enhance the transparency... 

Owing to a new platform for high performance and general-purpose computing, graphics processing unit (GPU) is one of the most promising candidates for faster improvement in peak processing speed, low latency and high performance. As GPUs employ multithreading to hide latency, there is a small private data cache in each single instruction multiple thread (SIMT) core. Hence, these cores communicate in many applications through the global memory. Access to this public memory takes long time and consumes large amount of power. Moreover, the memory bandwidth is limited which is quite challenging in parallel processing. The missed memory requests in last level cache that are followed by accesses... 

Allocating the scratchpad memory (SPM) space to tasks is a challenging problem in real-time multicore embedded systems that use shared SPM. Proper SPM space allocation is important, as it considerably influences the application worst-case execution time (WCET), which is of great importance in real-time applications. To address this problem, in this article we present a dynamic SPM reuse scheme, where SPM space can be reused by other tasks during runtime without requiring any static SPM partitioning. Although the proposed scheme is applied dynamically at runtime, the required decision making is fairly complex and hence cannot be performed at runtime. We have developed techniques to perform... 

We propose a new optical reconfigurable Network-on-Chip (NoC), named ReFaT ONoC (Reconfigurable Flat and Tree Optical NoC). ReFaT is a dynamically reconfigurable architecture, which customizes the topology and routing paths based on the application characteristics. ReFaT, as an all-optical NoC, routes optical packets based on their wavelengths. For this purpose, we propose a novel architecture for the optical switch, which eliminates the need for optical resource reservation, and thus avoids the corresponding latency and area overheads. As a key idea for dynamic reconfiguration, each application is mapped to a specific set of wavelengths and utilizes its dedicated routing algorithm. We... 

Phase Change Memory (PCM) is emerging as a high-dense and power-efficient choice for future main memory systems. While PCM cell size is marching towards minimum achievable feature size, recent prototypes effectively improve device scalability by storing multiple bits per each cell. Unfortunately, Multi-Level Cell (MLC) PCM devices offer higher access time and energy when compared to Single-Level Cell (SLC) counterparts making it difficult to incorporate MLC in main memory. To address this challenge, we proposes Zero-value-based Morphable PCM, ZM-PCM for short, a novel MLC-PCM main memory architecture which tries incorporating benefits of both MLC and SLC devices within the same structure.... 

Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient fault-tolerant scheme, called cache-assisted duplicated SPM (CADS), to protect SPM against soft errors. The main aim of CADS is to utilize cache memory to provide a replica for SPM lines. Using cache memory, CADS is able to guarantee a full duplication of all SPM lines. We also further enhance the proposed scheme by presenting buffered CADS (BCADS) that significantly improves the CADS energy efficiency. BCADS is compared with two well-known... 

The emergence of new memory technologies provides us with opportunity to enhance the properties of existing memory architectures. One such technology is Phase Change Memory (PCM) which boasts superior scalability, power savings, non-volatility, and a performance competitive to Dynamic Random Access Memory (DRAM). In this paper, we propose a write buffer architecture for Solid-State Drives (SSDs) which attempts to exploit PCM as a DRAM alternative while alleviating its issues such as long write latency, high write energy, and finite endurance. To this end and based on thorough I/O characterization of desktop and enterprise applications, we propose a hybrid DRAM-PCM SSD cache design with an... 

Several unicast and multicast routing protocols have been presented for MPSoCs. Multicast protocols in NoCs are used for cache coherency in distributed shared memory systems, replication, barrier synchronization, or clock synchronization. Unicast routing algorithms are not suitable for multicast, as they increase traffic, congestion and deadlock probability. Famous multicast schemes such as tree-based and path-based schemes have been proposed originally for multicomputers and recently adapted to NoCs. In this paper, we propose a switch tree-based multicast scheme, called STBA. This method supports tree construction with a minimum number of routers. Our evaluation results reveal that, for... 

With the emergence of Non-Volatile Memories (NVMs) and their shortcomings such as limited endurance and high power consumption in write requests, several studies have suggested hybrid memory architecture employing both Dynamic Random Access Memory (DRAM) and NVM in a memory system. By conducting a comprehensive experiments, we have observed that such studies lack to consider very important aspects of hybrid memories including the effect of: a) data migrations on performance, b) data migrations on power, and c) the granularity of data migration. This paper presents an efficient data migration scheme at the Operating System level in a hybrid DRAM-NVM memory architecture. In the proposed... 

Main burdens to the DRAM scalability are leakage and charge storage restrictions. Phase Change Memory (PCM) is being known as a promising candidate for the replacement of DRAM among competitive non-volatile memories. However, this memory suffers from low cell reliability due to limited write endurance. This problem can lead to some memory cells permanently stuck at either '0' or '1'. Therefore, a robust error recovery scheme is needed to overcome this problem and recover from hard errors. State-of-the-art solutions apply error correction and recovery techniques at inter-line or intra-line level. Precisely, they can improve PCM endurance either by remapping failed lines to spares (in... 

SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power. The main problem of utilizing NVMs across the SPM is their limited number of write cycles (endurance). This problem threatens the reliability of NVM-based SPMs. To alleviate the problem of limited endurance in NVM-based SPMs, this paper proposes a method, called overwrite purging through in-execution memory address snooping (OPTIMAS). The main idea behind the proposed method is to control the lifetime of NVM-based SPMs, directly by a hardware unit, outside of the SPM mapping algorithm. This idea... 

Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems. Many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories. However, accessing these memories imposes performance and energy overhead and using them as the code memory could increase the worst case execution time of the system. In this paper, a new code memory architecture for non-volatile memories is proposed which reduces the effective memory access latency by employing memory access interleaving technique. Unlike common instruction access latency improvement techniques such as prefetching and... 

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance... 

Storage subsystem is considered as the performance bottleneck of computer systems in data-intensive applications. Solid-State Drives (SSDs) are emerging storage devices which unlike Hard Disk Drives (HDDs), do not have mechanical parts and therefore, have superior performance compared to HDDs. Due to the high cost of SSDs, entirely replacing HDDs with SSDs is not economically justified. Additionally, SSDs can endure a limited number of writes before failing. To mitigate the shortcomings of SSDs while taking advantage of their high performance, SSD caching is practiced in both academia and industry. Previously proposed caching architectures have only focused on either performance or endurance... 

I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss...