Sharif Digital Repository

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch... 

One of the important yet insufficiently studied subjects in fair allocation is the externality effect among agents. For a resource allocation problem, externalities imply that the share allocated to an agent may affect the utilities of other agents. In this paper, we conduct a study of fair allocation of indivisible goods when the externalities are not negligible. Inspired by the models in the context of network diffusion, we present a simple and natural model, namely network externalities, to capture the externalities. To evaluate fairness in the network externalities model, we generalize the idea behind the notion of maximin-share (MMS) to achieve a new criterion, namely,... 

Data center performance is affected by three main factors; bandwidth, latency, and reliability of intra-data center interconnection network. Bandwidth and latency are definitely improved by adopting optical technology for intra-data center communication, but fault tolerance of the corresponding optical networks has been raised less. Recently, we introduced two Torus-based, all-optical, and non-blocking networks, i.e. O-TF and O-FTF, addressing reliability of optical networks, and now, in this paper, to address the scalability problem, we propose a novel Optical Clos-based architecture which reduces minimum number of required wavelength channels, as well as, the switch size in each node.... 

Synchronization of two coupled Chen systems through one of their variables is experimentally studied in this paper. We explore the chaotic behavior of the rescaled Chen system by the bifurcation analysis and computing its Lyapunov exponents which these results are also verified by circuitry realization of the system. Also, using 0-1 test, the chaotic manner of the circuit signals is validated. Finally, we synchronize two Chen circuits using unidirectional continues coupling with only one state variable and show despite the presence of the noise and the fact that two implemented circuits are not completely identical; the circuits achieve complete synchronization. © ICROS  

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the... 

Due to fast growth of wireless mobile networks, video transmission over wireless media has been widely studied. As wireless networks are error prone, there is a high possibility of loss in sent packets. Since time limitations in real-time video applications should be met, the delay-related to resending packets is not acceptable and the error should to be concealed at receiver side. With respect to different concealment methods, two new methods for temporal error concealment are proposed. In the first method, an optimized set of motion vectors is formed using motion vectors in surrounding blocks of the lost macroblock, and then this set is searched for the best motion vector. For extending... 

We present the results on the correlation between the flux to voltage transfer function, Vspp, of the rf-SQUID and the rf-bias frequency as well as rf-bias power. Measurements were performed for different SQUID gradiometer samples chosen from the same batch or different batches. In order to have full control on the electronics parameters, an experimental rf-SQUID circuit was designed and implemented with an operation frequency of 600 MHz to 900 MHz. According to our findings, It has been observed that at any particular rf-bias power, Vspp vs. rf-bias frequency shows Sine-like behavior. We observed that the main lobe maxima exist close to the resonance frequency of the LC tank circuit and by... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

Using network analysis, we investigate if an industry's complex and integrated knowledge base leads to a higher spatial concentration (or dispersal)of innovative activities. This is important because the extant literature provides competing claims about how knowledge base complexity impacts on the spatial distribution of industrial innovation. To help empirically resolve this issue, we draw on longitudinal data (1970–2010)on the upstream petroleum industry and build indexes of entropy and complexity to render knowledge base dynamics, assess the spatial concentration of innovation, and study industry structural transformations. We first find a correlation – once a crucial distinction between... 

In an ac microgrid, a common frequency exists for coordinating active power sharing among droop-controlled sources. A common frequency is absent in a dc microgrid, leaving only the dc source voltages for coordinating active power sharing. That causes sharing error and poorer voltage regulation in dc microgrids, which in most cases, are solved by a secondary control layer reinforced by an extensive communication network. To avoid such an infrastructure and its accompanied complications, this paper proposes an alternative droop scheme for low-voltage dc microgrid with both primary power sharing and secondary voltage regulation merged. The main idea is to introduce a non-zero unifying frequency... 

The shortest path problem is a classical and important network optimization problem appearing in many applications. We discuss the shortest path problem from a specified vertex to every other vertex on a network with imprecise arc lengths as fuzzy numbers. Using an order relation between fuzzy numbers, we propose a new algorithm to deal with the fuzzy shortest path problem. The algorithm is composed of a fuzzy shortest path length procedure and a similarity measure. The fuzzy shortest length method is proposed to find the fuzzy shortest length, and the fuzzy similarity measure is utilized to get the shortest path. Two illustrative examples are worked out to demonstrate the proposed algorithm... 

Solid State Drives (SSDs) have recently emerged as a high speed random access alternative to classical magnetic disks. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-flash standards to respond to ever increasing application demands. In this paper, we first give a deep look at how different flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement... 

The paper presents a vector model for a Brushless Doubly-Fed Machine (BDFM). The BDFM has 4 and 8 pole stator windings and a nested-loop rotor cage. The rotor cage has six nests equally spaced around the circumference and each nest comprises three loops. All the rotor loops are short circuited via a common end-ring at one end. The vector model is derived based on the electrical equations of the machine and appropriate vector transformations. In contrast to the stator, there is no three phase circuit in the rotor. Therefore, the vector transformations suitable for three phase circuits can not be utilised for the rotor circuit. A new vector transformation is employed for the rotor circuit... 

Flooding algorithm is one of the most significant algorithms used in sensor networks. Although simple, this algorithm causes a large amount of energy and bandwidth to be wasted. The most important application of flooding is RREQ flooding in initial step of most routing algorithms. Although simple, this algorithm causes a large amount of energy and bandwidth to be wasted. Most previous efficient flooding algorithms use location information which is impossible for simple node in sensor network. Some others are not suitable for RREQ flooding due to eliminating redundant retransmissions. We present a modified flooding that simultaneously decreases energy consumption as well as network delay.... 

The main contribution of this paper is utilizing bio-inspired evolutionary algorithm for reliability oriented high level synthesis. In this paper genetic algorithm is used to schedule a data-flow graph considering latency and resource allocation considering resource constraints and area overhead. Then a co-evolutionary strategy merges the results of these solutions to find the RT level design of the circuit which satisfies both performance and area constraints. To satisfy the user-defined reliability, another genetic algorithm is developed to insert some hardware redundancies to the resulted data-path. Experimental results show using the proposed approach results in an acceptable reliability... 

Communications in organizations have been one of the most important issues. To run the business processes, the company needs communication between units and customers. We provide a framework which can be used by network designers in an organization. The outcome of the framework is value for three QoS parameters: delay, loss and availability. The organizations business processes are used as a basis for the framework We used UML as the tool to model the business processes in the organization. First, the process is modeled with UML activity, sequence and class diagrams. Then, a three-step analysis has been conducted on the models to find the specifications of the business process. The analysis... 

With anticipated proliferation of electric vehicles and distributed generations in near future, dynamic thermal rating (DTR) as a tool for unlocking network capacities, is becoming critical for distribution network operators. DTR is gaining a great and still growing focus of attention in today's power industries. However, potential benefits of DTR, although have been envisioned to be significant, have not yet been studied quantitatively. This paper intends to comprehensively assess the potential impacts of DTR on the performance of a realistic Finnish distribution network. For doing so, first a step-by-step procedure is devised. Then, weather data and loading information of circuits in the... 

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between... 

It has been attempted to gain a new viewpoint in transient cell modeling of vanadium redox flow battery. This has been achieved by considering electrochemical relations along with conceptual electrical circuit of this kind of battery. The redox flow battery is one of the best rechargeable batteries because of its capability to average loads and output power sources. A model of transient behavior is presented in this paper. The transient features are considered as the most remarkable characteristics of the battery. The chemical reactions, fluid flow, and electrical circuit of the structure govern the dynamics. The transient behavior of the redox flow battery based on chemical reactions is... 

Optical networks-on-chip are introduced as an alternative for electrical interconnects in many-core systems, due to their low delay and power consumptions, as well as their high bandwidths. Despite these advantages, physical characteristics of the photonic components are highly sensitive to thermal variations, which results in optical data misrouting through the optical networks at the presence of temperature fluctuation. In this paper, we propose a thermally-resilient all-optical communication approach which improves reliability, as well as performance of the optical networks. For this purpose, we take advantages of auxiliary waveguides and a novel wavelength assignment approach to avoid...