Search for: reconfigurable-hardware
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    A low-power high-speed comparator for analog to digital converters

    , Article 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 2010-2013 ; 02714310 (ISSN); 9781479953400 (ISBN) Khorami, A ; Baraani Dastjerdi, M ; Fotowat Ahmadi, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power... 

    A novel optimization method based on opinion formation in complex networks

    , Article 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 882-885 ; 02714310 (ISSN); 9781479953400 (ISBN) Hamed Moghadam Rafati, H ; Jalili, M ; Yu, X ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    In this paper we introduce a novel population-based binary optimization technique, which works based on consensus of interacting multi-agent systems. The agents, each associated with an opinion vector, are connected through a network. They can influence each other, and thus their opinions can be updated. The agents work collectively with their neighbors to solve an optimization task. Here we consider a specific opinion update rule and various topologies for the connection network. Our experiments on a number of benchmark non-convex cost functions show that ring topology results in the best performance as compared to others. We also compare the performance of the proposed method with a number... 

    An isolated bidirectional integrated plug-in hybrid electric vehicle battery charger with resonant converters

    , Article Electric Power Components and Systems ; Volume 44, Issue 12 , 2016 , Pages 1371-1383 ; 15325008 (ISSN) Ebrahimi, S ; Akbari, R ; Tahami, F ; Oraee, H ; Sharif University of Technology
    Taylor and Francis Inc  2016
    Plug-in hybrid electric vehicles draw electricity from the electrical grid and store energy in their batteries. To increase charge availability for plug-in hybrid electric vehicles, on-board chargers can be used, which should be small in size and lightweight. In this article, an on-board bidirectional soft-switched battery charger is proposed that utilizes a phase-shift-controlled dual-bridge series resonant converter with isolation. The bidirectional characteristic of proposed charger makes it suitable for vehicle-to-grid operation (i.e., injecting power from the vehicle to the grid) in smart grids. A switching control scheme is also proposed to provide soft-switching operation for all... 

    Energy harvesting via shallow cylindrical and spherical piezoelectric panels using higher order shear deformation theory

    , Article Composite Structures ; Volume 147 , 2016 , Pages 155-167 ; 02638223 (ISSN) Sayyaadi, H ; Rahnama, F ; Askari Farsangi, M. A ; Sharif University of Technology
    Elsevier Ltd 
    In this article an analytical solution is presented for power output from a piezoelectric shallow shell energy harvester using higher order shear deformation theory (HSDT). The energy harvester is made of an elastic substrate layer coupled with one or two surface bonded piezoelectric layers. Mechanical equations of motion with Gauss's equation are derived on the basis of HSDT and solved simultaneously for simply-supported mechanical boundary conditions. The electromechanical frequency response functions that relate the power output and circuit load resistance are identified from the exact solutions. Using Rayleigh damping the influence of structural damping is taken into account. Also... 

    High-speed low-power comparator for analog to digital converters

    , Article AEU - International Journal of Electronics and Communications ; Volume 70, Issue 7 , 2016 , Pages 886-894 ; 14348411 (ISSN) Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Elsevier GmbH 
    A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

    Reliability-aware design to suppress aging

    , Article 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, 5 June 2016 through 9 June 2016 ; Volume 05-09 , June-2016 , 2016 ; 0738100X (ISSN); 9781450342360 (ISBN) Amrouch, H ; Khaleghi, B ; Gerstlauerz, A ; Henkel, J ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this paper, we propose to bring aging awareness to EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on both threshold voltage (Vth) and carrier mobility (μ) of transistors. This is unlike state of the art which considers Vth only. We show how ignoring μ degradation leads to underestimating guard-bands by 19% on average. Our investigation revealed that the impact of aging is strongly dependent on the... 

    A broadband integrated class-J power amplifier in gaas pHEMT technology

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 64, Issue 6 , 2016 , Pages 1822-1830 ; 00189480 (ISSN) Alizadeh, A ; Medi, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence of nonlinear drain-source resistance of transistors (RDS). A procedure is developed for ideal transistor sizing where transistors are concurrently stabilized and sized to achieve the maximum power-added efficiency (PAE). A 3.5-7 GHz, 0.5-W class-J PA is implemented in a 0.1-μm AlGaAs-InGaAs pHEMT technology to check the accuracy of the proposed approach. With chip dimensions of 1.57 × 1.29 mm2, the PA achieves 56% average PAE over the frequency... 

    Reconfigurable multicast routing for Networks on Chip

    , Article Microprocessors and Microsystems ; Volume 42 , 2016 , Pages 180-189 ; 01419331 (ISSN) Nasiri, F ; Sarbazi Azad, H ; Khademzadeh, A ; Sharif University of Technology
    Several unicast and multicast routing protocols have been presented for MPSoCs. Multicast protocols in NoCs are used for cache coherency in distributed shared memory systems, replication, barrier synchronization, or clock synchronization. Unicast routing algorithms are not suitable for multicast, as they increase traffic, congestion and deadlock probability. Famous multicast schemes such as tree-based and path-based schemes have been proposed originally for multicomputers and recently adapted to NoCs. In this paper, we propose a switch tree-based multicast scheme, called STBA. This method supports tree construction with a minimum number of routers. Our evaluation results reveal that, for... 

    Thermal and power aware task mapping on 3D Network on Chip

    , Article Computers and Electrical Engineering ; Volume 51 , 2016 , Pages 157-167 ; 00457906 (ISSN) Mosayyebzadeh, A ; Mehdizadeh Amiraski, A ; Hessabi, S ; Sharif University of Technology
    Elsevier Ltd 
    High integration and increased elements density in 3D Network on Chip (NoC) will cause more energy consumption and high temperature on chip. By mapping those tasks that have data communication between them to near cores, the communication delay and therefore, power consumption will be reduced. In addition, mapping the tasks to cores that are near the heat sink, in such a way that the generated heat is distributed indiscriminately all over the chip, will decrease maximum chip temperature. In this paper, we propose a task mapping method based on fuzzy logic that aims to alleviate power and thermal problems in 3D-NoCs. In this method, the weight of task mapping factors can be changed according... 

    Potential of light-harvesting of bacteriorhodopsin co-sensitized with green fluorescence protein: A new insight into bioenergy application

    , Article Biomass and Bioenergy ; Volume 87 , 2016 , Pages 35-38 ; 09619534 (ISSN) Mohammadpour, R ; Janfaza, S ; Zeinoddini, M ; Sharif University of Technology
    Elsevier Ltd  2016
    Herein we report for the first time on efficient and environmentally friendly bioenergy production from bacteriorhodopsin (bR) and green florescent protein (GFP) as co-sensitizers. bR as a transmembrane protein, acts like a light-driven proton pump in Halobacterium salinarum, converting light energy into a proton gradient. Employing GFP beside bR can enhance the photo-bioenergy production efficiency in two aspects: GFP can increase short circuit current by improvement in light absorption either by extending the sensitizingspectrumor making fluorescence in absorption region of bR. It can also enhance open circuit voltage more than 150 mV by improvement in photoelectrode converging and... 

    A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application

    , Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) Molaei, H ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

    PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era

    , Article IEEE Transactions on Computers ; Volume 66, Issue 6 , 2017 , Pages 982-995 ; 00189340 (ISSN) Ebrahimi, Z ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2017
    Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of... 

    A dynamic method for feeder reconfiguration and capacitor switching in smart distribution systems

    , Article International Journal of Electrical Power and Energy Systems ; Volume 85 , 2017 , Pages 200-211 ; 01420615 (ISSN) Ameli, A ; Ahmadifar, A ; Shariatkhah, M. H ; Vakilian, M ; Haghifam, M. R ; Sharif University of Technology
    Elsevier Ltd  2017
    In distribution systems, feeder reconfiguration (FR) can lead to loss reduction, reliability improvement and some other economic savings. These advantages can be intensified by proper control and switching of Capacitor Banks (CBs). In this paper, using Ant Colony Optimization (ACO) technique, a novel method is proposed for simultaneous dynamic scheduling of FR and CB switching in the presence of DG units having uncertain and variant generations over time. This method is applicable to both smart and classic distribution systems. While for the latter, state estimation method should be used to estimate the loads at different buses by employing a limited number of measurements. The objective of... 

    Evaluation of FPGA Hardware as a New Approach for Accelerating the Numerical Solution of CFD Problems

    , Article IEEE Access ; Volume 5 , 2017 , Pages 9717-9727 ; 21693536 (ISSN) Ebrahimi, A ; Zandsalimy, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    The main purpose of this paper is to investigate the feasibility of using field programmable gate arrays (FPGAs) chips as alternatives for the conventional CPUs to accelerate the numerical solution of the fluid dynamics differential equations. FPGA is an integrated circuit that contains an array of logic blocks, and its architecture can be reprogrammed and reconfigured after manufacturing. Complex circuits for various applications can be designed and implemented using FPGA hardware. The reconfigurable hardware used in this paper is a system on a chip FPGA type that integrates both microprocessor and FPGA architectures into a single device. In this paper, typical computational fluid dynamics... 

    Modeling and simulation speed-up of plasma actuators implementing reconfigurable hardware

    , Article AIAA Journal ; Volume 56, Issue 8 , 2018 , Pages 3035-3046 ; 00011452 (ISSN) Ebrahimi, A ; Zandsalimy, M ; Sharif University of Technology
    American Institute of Aeronautics and Astronautics Inc  2018
    The objective of the present study is to investigate the capability of field-programmable gate array hardware in numerical simulation of a model of a dielectric barrier discharge plasma actuator to accelerate the calculations. The reconfigurable hardware is designed such that it is possible to reprogram its architecture after manufacturing. This provides the capability to design and implement various architectures for several applications. Two reconfigurable chips are used in the present study, one of which consists of a programmable logic unit and a typical microprocessor. This hybrid architecture makes the high performance of the reconfigurable hardware in custom computing and the... 

    A unified approach to detect and distinguish hardware trojans and faults in sram-based fpgas

    , Article Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 35, Issue 2 , 2019 , Pages 201-214 ; 09238174 (ISSN) Ranjbar, O ; Bayat Sarmadi, S ; Pooyan, F ; Asadi, H ; Sharif University of Technology
    Springer New York LLC  2019
    In recent years, confrontation with hardware Trojans has become a major concern due to various reasons including outsourcing. Such a growing threat is more pronounced in reconfigurable devices as they are used in widespread applications due to low design cost and short time-to-market. Besides their vulnerability to hardware Trojan attacks, SRAM-based reconfigurable devices are also significantly susceptible to faults originated by particle strikes. There have been various methods to mitigate either hardware Trojan attacks or faults. To our knowledge, however, no method has been presented that can integrate detecting, distinguishing, and mitigating faults and Trojans. In this paper, we... 

    CNTFET full-adders for energy-efficient arithmetic applications

    , Article 6th International Conference on Computing, Communications and Networking Technologies, 13 July 2015 through 15 July 2015 ; 2015 ; 9781479979844 (ISBN) Grailoo, M ; Hashemi, M ; Haghshenas, K ; Rezaee, S ; Rapolu, S ; Nikoubin, T ; University of North Texas ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm... 

    Modeling comparison of graphene nanoribbon field effect transistors with single vacancy defect

    , Article Superlattices and Microstructures ; Volume 97 , 2016 , Pages 28-45 ; 07496036 (ISSN) Nazari, A ; Faez, R ; Shamloo, H ; Sharif University of Technology
    Academic Press  2016
    In this paper, some important circuit parameters of a monolayer armchair graphene nanoribbon (GNR) field effect transistor (GNRFET) in different structures are studied. Also, these structures are Ideal with no defect, 1SVGNRFET with one single vacancy defect, and 3SVsGNRFET with three SV defects. Moreover, the circuit parameters are extracted based on Semi Classical Top of Barrier Modeling (SCTOBM) method. The I-V characteristics simulations of Ideal GNRFET, 1SVGNRFET and 3SVsGNRFET are used for comparing with SCTOBM method. These simulations are solved with Poisson-Schrodinger equation self-consistently by using Non- Equilibrium Green Function (NEGF) and in the real space approach. The...