Sharif Digital Repository

In this brief, we present a fine-grained dark silicon architecture to facilitate further integration of transistors in static random access memory-based reconfigurable devices. In the proposed architecture, we present a technique to power off inactive configuration cells in nonutilized or underutilized logic blocks. We also propose a routing circuitry capable of turning off the configuration cells of connection blocks (CBs) and switch boxes (SBs) in the routing fabric. Experimental results carried out on the Microelectronics Center of North Carolina benchmark show that power consumption in configuration cells of lookup tables, CBs, and SBs can, on average, be reduced by 27%, 75%, and 4%,... 

Flow behavior of two grades of steel including a high silicon (HS) steel and a plain low carbon steel as the reference were considered in this work. Tensile testing at temperatures varying between 25 and 550 °C and different strain rates in the range of 4×10-5 to 0.1 s-1 were conducted and the mechanical properties, such as elongation at fracture point and strain rate sensitivity were then determined. It is observed that for both steels, dynamic strain aging occurs in the employed deformation conditions, however, the region of serrated flow and the type of the serration were somehow different. For the case of the HS steel, the serrated flow region is shifted to the higher temperatures and... 

Core specialization is a promising solution to the dark silicon challenge. This approach trades off the cheaper silicon area with energy-efficiency by integrating a selection of many diverse application-specific cores into a single billion-transistor multicore chip. Each application then activates the subset of cores that best matches its processing requirements. These cores act as a customized application-specific CMP for the application. Such an arrangement of cores requires some special on-chip inter-core communication treatment to efficiently connect active cores. In this paper, we propose a reconfigurable network-on-chip that leverages the routers of the dark portion of the chip to... 

Diurnal volume changes is one of the main factors influencing socket fit in trans-tibial prosthesis and causing pressure problem issues. Embedded bladder liners have been recently a potential approach to deal with this problem. The aim of this technical note was to introduce a new transtibial silicone liner designed based on hybrid socket theory. To make expandability in the liner, an integrated wax structure was constructed over the selected areas of the positive model and then removed after lamination process. In addition, a mechanical system with manual control was designed to fit the liner with the residual limb volume by pumping the water in or out of the liner through connec-tive... 

Porous silicon samples were obtained from p+- and n-type silicon wafers. Gas sensing measurements showed that the electrical conductivity of porous Si on p+- and n-type wafers increases strongly and decreases weakly in the presence of methanol gas, respectively. Scanning tunneling spectroscopy (STS) indicates that the adsorption of methanol on the surface of n-porous silicon decreases the average density of states especially in the band gap. Fourier transform infrared (FTIR) spectroscopy reveals that after methanol exposure partial surface oxidation occurs which produces electron traps as well as methanol adsorption on the porous surfaces. These observations imply that the number of... 

In this paper, we present the room temperature current-voltage characteristics of large (100×100 μ m2) and a nanoscale (100×100 nm2) metal-oxide-semiconductor (MOS) capacitor containing few silicon nanocrystals. The layer of silicon crystals is synthesized within the oxide of this capacitor by ultralow energy ion implantation and annealing. Current fluctuations in the form of discrete current steps and sharp peaks are apparent in the static and dynamic I (V) characteristics of the capacitor. These features have been associated to quantized charging and discharging of the nanoparticles and the resulting Coulomb interaction to the tunneling current. © 2005 American Vacuum Society  

We prepared porous silicon samples coated by continuous palladium layer in electroless process. Scanning electron microscopy (SEM) showed cauliflower-shape Pd clusters on the surface. I–V curves of Schottky like Pd/porous Si samples were measured in air and in hydrogen. These measurements showed a metal–interface–semiconductor configuration rather than an ideal Schottky diode. Variations of the electrical current in the presence of diluted hydrogen at room temperature revealed that the samples can sense hydrogen in a wide range of concentration (100–40,000 ppm) without any saturation behavior. Hydrogen sensing properties of these samples were investigated at room temperature for a duration... 

The band gap offset is an effect of coordination numbers (CNs) of atom reduction at the edge of transversal cross-section of Silicon nanowires (SiNWs). In this paper, a hierarchical multi-scale technique is developed to model the edge effect on the band gap shift of SiNWs since the geometric effect is dominant in the energy gap due to the appearance of strain in the self-equilibrium state. The multi-scale model is performed based on the molecular dynamics approach and finite element method for the micro- (atomistic) and macro-scale levels, respectively. The Cauchy–Born (CB) hypothesis is used to relate the atomic positions to the continuum field through the deformation gradient. Finally, the... 

In this paper, simulative study on the effects of lattice temperature on a GaInP/6H-SiC strained quantum-well (QW) laser's device is presented. Loss mechanisms are severe in the edge-emitting lasers. As a consequence, the wall-plug efficiency is sensitive to changes in temperature. The lasers used in this work were separate-confinement quantum-well lasers with a single strained GaInP, located in a latticematched waveguide core and cladding region of 6H-SiC. This paper provides the key results of the wall-plug efficiency upon the lattice temperature  

The effects of the mold preheating and the silicon content of ductile iron on the percentage of carbides, graphite nodule counts and shrinkage volume were investigated. The results showed that the percentage of carbides and the shrinkage volume decreased when the mold preheating increased. The ductile iron with the carbon equivalent of 4.45% and the silicon content of 2.5% without any porosity defects was achieved when the mold preheating was 450 °C. Increasing the silicon content in the range of 2.1%-3.3% led to the increase in graphite nodule count and graphite size and the decrease in percentage of carbides. It is due to the increase in induced expansion pressure during the graphite... 

A new triple-component sensor for detection of H2 was developed based on porous silicon and CNTs. An increase in deposition of CVD catalysis was shown to promote a high and fast response. Also, it was shown that the composite system exhibited good selectivity  

The increased leakage power of deep-nano technologies in the one hand, and exponential growth in the number of transistors in a given die particularly in Field-Programmable Gate Arrays (FPGAs) have resulted in an intensified rate of static power dissipation as well as power density. This ever-increasing static power consumption acts as a power wall to further integration of transistors and has caused the breakdown of Dennard scaling. To meet the available power budget and preclude reliability challenges associated with high power density, designers are obligated to restrict the active percentage of the chip by powering off a selective fraction of silicon die, referred to as Dark Silicon.... 

For many years, computer designers benefitted from Moore's law and Dennard scaling to significantly improve the speed of single-core processors. The failure of Dennard scaling pushed the computer industry toward homogenous multicore processors for the performance improvement to continue without significant increase in power consumption. Unfortunately, even homogeneous multicore processors cannot offer the level of energy efficiency required to operate all the cores at the same time in today's and especially tomorrow's technologies. As a result of lack of energy efficiency, not all the cores in a multicore processor can be functional at the same time. This phenomenon is referred to as dark... 

Low silicon content SAPO-34 was successfully synthesized using the conventional hydrothermal crystallization in the static condition. Effects of different synthesis conditions including crystallization temperature and the silicon source were investigated through X-ray diffraction patterns. It was concluded that the silicon source had a significant effect on silicon incorporation into the alumino-phosphate building blocks in the course of crystallization. Using precipitated silica instead of silica sol resulted in the formation of impurities of alumino-phosphates phases whose crystalline structures collapse at the high temperature of calcination. For the low silicon SAPO-34 synthesis, the...