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In this note, bounded-input bounded-output (BIBO)-stability of a large class of neutral type fractional delay systems is investigated. Necessary and sufficient conditions of BIBO-stability are presented for the intended class of systems (the sufficient conditions have been provided for a more general case in the previous studies). Two lemmas are provided for checking a prerequisite imposed on the considered class of systems. Finally, two numerical examples are given to illustrate the obtained results  

This paper considers a closed-loop system consisting of a fractional/integer order system and a fractional PID controller. Assuming that the uncertain coefficients of the fractional PID controller lie in some known intervals independently (i.e. that controller is a member of an interval family), the paper presents some easy to use theorems to investigate the robust bounded-input bounded-output stability of the resultant closed-loop system. Moreover, a finite frequency bound required in drawing the related graphs has also been provided. Finally, some numerical examples are presented to illustrate the results  

In this paper, the computation of robustness margin for linear time invariant fractional order systems is studied. For the definition of robustness margin, we employ the one introduced for polynomials (i.e. integer order) and extend it to fractional order functions. Using the well known concept of the value set and knowing its shape for the intended functions, this paper presents an easy way to obtain the robustness margin for fractional order systems. To illustrate the results, a numerical example is provided  

This paper deals with the analysis of robust BIBO-stability of LTI fractional order delay systems in the presence of real parametric uncertainties. Two large classes of these systems, namely retarded and neutral types, are considered. Two theorems are given to check the robust BIBO-stability of these two families of fractional order systems. One of these theorems provides necessary and sufficient conditions for the case of retarded type and another one presents only sufficient conditions for the case of neutral type. Furthermore, upper and lower bounds (cutoff frequencies) are provided for drawing the value sets. To illustrate the results, two numerical examples are presented  

Robustness of a fractional proportional-integral-derivative (PID)-based control system is investigated. At first the largest pathwise connected region subset of a box in three-dimensional space of the parameters of the model is determined such that the closed-loop system is bounded-input bounded-output stable for any point inside it. Then a value that represents the size (in a specified sense) of the calculated region in the first stage and can be considered as a margin for the robustness of the closed-loop system is computed. Furthermore, lower and upper frequency bounds required in depiction of boundaries of the region and computing the mentioned margin are provided. Some special cases in... 

This study deals with the subject of robust bounded-input bounded-output (BIBO)-stability of a family of fractional order interval systems. Employing the idea of'robust stability testing function'and extending it to the case of intended systems, a simple graphical procedure for checking the robust BIBO-stability applicable to both commensurate and incommensurate orders is developed. Moreover, a Kharitonov-like theorem is provided that presents necessary and sufficient conditions for checking the mentioned stability of the fractional order interval systems with commensurate order α belonging to [1,2), but only sufficient conditions for commensurate order α in interval (0,1). Besides, lower... 

In this paper, the robust bounded-input bounded-output stability of a large class of linear time invariant fractional order families of systems with real parametric uncertainties is analyzed. The transfer functions contain polynomials in fractional powers of the Laplace variable s, possibly in combination with exponentials of fractional powers of s. Using the concept of the value set and a generalization of the zero exclusion condition theorem, a theorem to check the robust bounded-input bounded-output stability of these families of systems is presented. An upper cutoff frequency for drawing the value sets is provided as well. Finally, two numerical examples are given to illustrate results... 

For many years, computer designers benefitted from Moore's law and Dennard scaling to significantly improve the speed of single-core processors. The failure of Dennard scaling pushed the computer industry toward homogenous multicore processors for the performance improvement to continue without significant increase in power consumption. Unfortunately, even homogeneous multicore processors cannot offer the level of energy efficiency required to operate all the cores at the same time in today's and especially tomorrow's technologies. As a result of lack of energy efficiency, not all the cores in a multicore processor can be functional at the same time. This phenomenon is referred to as dark... 

Many applications, including big-data server applications, frequently encounter data misses. Consequently, they lose significant performance potential. Fortunately, data accesses of many of these applications follow temporal correlations, which means data accesses repeat over time. Temporal correlations occur because applications usually consist of loops, and hence, the sequence of instructions that constitute the body of a loop repeats many times, leading to data access repetition. Temporal data prefetchers take advantage of temporal correlation to predict and prefetch future memory accesses. In this chapter, we introduce the concept of temporal prefetching and present two instances of... 

Many applications extensively use data objects with a regular and fixed layout, which leads to the recurrence of access patterns over memory regions. Spatial data prefetching techniques exploit this phenomenon to prefetch future memory references and hide their long latency. Spatial prefetchers are particularly of interest because they usually only need a small storage budget. In this chapter, we introduce the concept of spatial prefetching and present two instances of spatial data prefetchers, SMS and VLDP. © 2021 Elsevier Inc  

Many applications, including big-data server applications, frequently encounter data misses. Consequently, they lose significant performance potential. Fortunately, data accesses of many of these applications follow temporal correlations, which means data accesses repeat over time. Temporal correlations occur because applications usually consist of loops, and hence, the sequence of instructions that constitute the body of a loop repeats many times, leading to data access repetition. Temporal data prefetchers take advantage of temporal correlation to predict and prefetch future memory accesses. In this chapter, we introduce the concept of temporal prefetching and present two instances of... 

Many applications extensively use data objects with a regular and fixed layout, which leads to the recurrence of access patterns over memory regions. Spatial data prefetching techniques exploit this phenomenon to prefetch future memory references and hide their long latency. Spatial prefetchers are particularly of interest because they usually only need a small storage budget. In this chapter, we introduce the concept of spatial prefetching and present two instances of spatial data prefetchers, SMS and VLDP. © 2022 Elsevier Inc  

Knowing the exact position and rotation is a crucial necessity for the navigation of autonomous robots. Even in outdoor environments GPS signals are not always accessible for estimating online rotation and position of robots. Also inertial aided navigation methods have their own defects such as the drift of gyroscope or inaccuracy of accelerometer in agile motions and environmental sensitivity of compass. In this article, we have introduced a novel online visual gyroscope that can estimate the rotation of a moving car with analyzing the images of a monocular camera installed on it. Our real time visual gyroscope utilizes an efficient method of rotation estimation between each pair of camera... 

Side Channel Analysis (SCA) are still harmful threats against security of embedded systems. Due to the fact that every kind of SCA attack or countermeasure against it needs to be implemented before evaluation, a huge amount of time and cost of this process is paid for providing high resolution measurement tools, calibrating them and also implementation of proposed design on ASIC or target platform. In this paper, we have introduced a novel simulation platform for evaluation of power based SCA attacks and countermeasures. We have used Synopsys power analysis tools in order to simulate a processor and implement a successful Differential Power Analysis (DPA) attack on it. Then we focused on the... 

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

Server workloads benefit from execution on many-core processors due to their massive request-level parallelism. A key characteristic of server workloads is the large instruction footprints. While a shared last-level cache (LLC) captures the footprints, it necessitates a low-latency network-on-chip (NOC) to minimize the core stall time on accesses serviced by the LLC. As strict quality-of-service requirements preclude the use of lean cores in server processors, we observe that even state-of-the-art single-cycle multi-hop NOCs are far from ideal because they impose significant NOC-induced delays on the LLC access latency, and diminish performance. Most of the NOC delay is due to per-hop...