Sharif Digital Repository

We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller circuitry to restore the system to the fault-free state. As a case study, we have implemented the proposed ScTMR technique on an embedded processor, suited for safety-critical applications. Exhaustive fault injection experiments reveal that the proposed architecture has the error detection and... 

This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks... 

A method for simulation-emulation co-operation of Verilog and VHDL models is presented. The method is based on using Programming Language Interface (PLI) to achieve speedup in prototyping and to facilitate the communication between an emulator and a simulator. The PLI technique is implemented for both Verilog and VHDL models. The results show that this simulation-emulation co-operation method can significantly reduce the simulation time of a design implemented by VHDL codes as well as Verilog codes. © Springer-Verlag Berlin Heidelberg 2002  

This paper presents an analytical approach to estimate the speedup in a simulation-emulation cooperation environment. The speedup of this approach as compared with the speedup of a pure simulation is analyzed. Also, an analysis of the speedup is given when different types of application instructions are utilized. The analysis is based on using both Verilog and VHDL. The results show that when only the simulation part of the simulation-emulation co-operation is used, the speedup is higher, than when the pure simulation is used. The total speedup is also depended on the type of application instructions and the communication cycle time between the simulator and the emulator. © 2002 IEEE  

Although bioresorbable polymers have been used to produce guided bone regeneration (GBR) membranes for many years, the fabrication of such membranes with custom design was prevented by production limitations. However, in addition to less risk of infection and no need for membrane removal surgery, patient-specific resorbable membranes can significantly reduce installation difficulty, time of surgery, and patient's bleeding. This paper presented a novel method to design custom GBR membranes which are producible by the common 3D-bioprinters. Results showed acceptable geometrical accuracy and mechanical stability of the fabricated GBR membranes for covering the bone defect site in two real... 

This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest pans of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Co-operation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject... 

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits' combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection... 

In this paper, we present a scan-chain-based multiple error recovery technique for triple modular redundancy (TMR) systems (SMERTMR). The proposed technique reuses scan-chain flip-flops fabricated for testability purposes to detect and correct faulty modules in the presence of single or multiple transient faults. In the proposed technique, the manifested errors are detected at the modules' outputs, while the latent faults are detected by comparing the internal states of the TMR modules. Upon detection of any mismatch, the faulty modules are located and the state of a fault-free module is copied into the faulty modules. In case of detecting a permanent fault, the system is degraded to a... 

Despite widespread use of SRAM-based reconfigurable devices (SRDs) in mainstream applications, their usage has been very limited in enterprise and safety-critical applications due to SRAM susceptibility to soft errors. Previous mitigation techniques to protect SRDs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to multiple bit upsets (MBUs). In this paper, we present a highly available fault-tolerant architecture to protect SRD-based designs against MBUs in both configuration and user bits. In the proposed architecture, the entire design is duplicated with respect to the relative locations of logic blocks within the SRD and... 

As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly... 

As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly... 

As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly... 

Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single... 

In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault injection approach with 92% accuracy. This makes the proposed approach applicable to industrial-scale circuits  

Erasure codes are widely used in data storage systems to protect against disk failures. Employing erasure codes in an array of Solid-State Drives (SSDs) in storage systems necessitates designers to revisit different characteristics in comparison to Hard Disk Drives (HDDs), due to non-mechanical property of SSDs. One of the most important characteristics of SSDs is their limitation on the number of Program/Erase (P/E) cycles. By taking into account the characteristics of SSDs, this paper presents a comprehensive analysis to investigate the effects of three well-known erasure codes on the endurance and performance of SSD-based disk subsystems. The three erasure codes, i.e., Reed-Solomon,... 

In this paper, we propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates,flip-flops, and paths of a circuit. Using such information, designers can selectively protect the vulnerable parts resulting in lower power and area overheads that are the most important factors in embedded systems. Unlike previous approaches, the proposed approach firstly does not rely on fault injection or fault simulation; secondly it measures the SER for multi cycles of circuit operation; thirdly, the proposed approach accurately computes all three masking factors, namely, logical, electrical, and timing masking; fourthly, the effects of error... 

In this research, the problems of adiabatic film-cooling the flat, convex, and concave surfaces are investigated numerically. Two different radii of curvature and one row of vertical injection holes are considered. The Navier-Stokes equations are solved using a fine nonuniform multiblock staggered curvilinear grid and the SIMPLE-based finite volume method. The blowing rates are 0.5 and 1.0 and the mainstream Reynolds number is 10,000. The obtained results indicated that at a low blowing ratio, the cooling effectiveness enhances over the convex surface and reduces over the concave surface compared to the flat surface case. In comparison with the low blowing ratio, the curvature effects at a... 

In this work, the rising of a single bubble in a quiescent liquid under microgravity condition was simulated. In addition to general studies of microgravity effects, the initiation of hydrodynamic convection, solely due to the variations of interface curvature (surface tension force) and thus the generation of shearing forces at the interfaces, was also studied. Then, the variation of surface tension due to the temperature gradient (Marangoni convection), which can initiate the onset of convection even in the absence of buoyancy, was studied. The related unsteady incompressible full Navier-Stokes equations were solved using a finite difference method with a structured staggered grid. The... 

SRAM-based FPGAs are currently utilized in applications such as industrial and space applications where high availability and reliability and low cost are important constraints. The technology of such devices is sensible to Single Event Upsets (SEUs) that may be originated mainly from heavy ion radiation. This paper presents a fault injection method that is based on emulated SEU on the configuration bitstrearn file of commercial SRAM-based FPGA devices to study the error propagation in these devices. To demonstrate the method, an Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used. A fault injection tool is developed to inject emulated SEU faults into the circuits.... 

The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device