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    A system-level framework for analytical and empirical reliability exploration of STT-MRAM caches

    , Article IEEE Transactions on Reliability ; Volume 69, Issue 2 , 2020 , Pages 594-610 Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In... 

    A system-level framework for analytical and empirical reliability exploration of stt-mram caches

    , Article IEEE Transactions on Reliability ; 2019 ; 00189529 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In... 

    A system-level framework for analytical and empirical reliability exploration of stt-mram caches

    , Article IEEE Transactions on Reliability ; 2019 ; 00189529 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In... 

    3RSeT: Read disturbance rate reduction in STT-mram caches by selective tag comparison

    , Article IEEE Transactions on Computers ; 2021 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2021
    Abstract
    Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to radiation-induced particles, and non-volatility, an unintentional bit flip during read operation, referred to as read disturbance error, is a severe reliability challenge in STT-MRAM caches. One major source of read disturbance error in STT-MRAM caches is simultaneous accesses to all tags for parallel comparison operation in a cache set, which has not been addressed in previous work. This paper first demonstrates that high read accesses to tag arrays extremely... 

    3RSeT: Read disturbance rate reduction in STT-MRAM caches by selective tag comparison

    , Article IEEE Transactions on Computers ; Volume 71, Issue 6 , 2022 , Pages 1305-1319 ; 00189340 (ISSN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2022
    Abstract
    Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to radiation-induced particles, and non-volatility, an unintentional bit flip during read operation, referred to as read disturbance error, is a severe reliability challenge in STT-MRAM caches. One major source of read disturbance error in STT-MRAM caches is simultaneous accesses to all tags for parallel comparison operation in a cache set, which has not been addressed in previous work. This article first demonstrates that high read accesses to tag array extremely... 

    Artificial intelligence and signal processing: International symposium, AISP 2013 Tehran, Iran, December 25-26, 2013 Revised selected papers

    , Article Communications in Computer and Information Science ; Vol. 427, issue , December , 2014 ; ISSN: 18650929 ; ISBN: 978-331910848-3 Movaghar, A ; Jamzad, M ; Asadi, H ; Sharif University of Technology
    2014
    Abstract
    [No abstract available]  

    An efficient reconfigurable architecture by characterizing most frequent logic functions

    , Article 25th International Conference on Field Programmable Logic and Applications, FPL 2015, 2 September 2015 through 4 September 2015 ; Sept , 2015 , Page(s): 1 - 6 ; 9780993428005 (ISBN) Ahmadpour, I ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity... 

    Evaluating impact of human errors on the availability of data storage systems

    , Article 20th Design, Automation and Test in Europe, DATE 2017, 27 March 2017 through 31 March 2017 ; 2017 , Pages 314-317 ; 9783981537093 (ISBN) Kishani, M ; Eftekhari, R ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    In this paper, we investigate the effect of incorrect disk replacement service on the availability of data storage systems. To this end, we first conduct Monte Carlo simulations to evaluate the availability of disk subsystem by considering disk failures and incorrect disk replacement service. We also propose a Markov model that corroborates the Monte Carlo simulation results. We further extend the proposed model to consider the effect of automatic disk fail-over policy. The results obtained by the proposed model show that overlooking the impact of incorrect disk replacement can result up to three orders of magnitude unavailability underestimation. Moreover, this study suggests that by... 

    PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era

    , Article IEEE Transactions on Computers ; Volume 66, Issue 6 , 2017 , Pages 982-995 ; 00189340 (ISSN) Ebrahimi, Z ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2017
    Abstract
    Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of... 

    ECI-cache: a high-endurance and cost-efficient I/O caching scheme for virtualized platforms

    , Article SIGMETRICS 2018 - Abstracts of the 2018 ACM International Conference on Measurement and Modeling of Computer Systems ; 12 June , 2018 , Pages 73- ; 9781450358460 (ISBN) Ahmadian, S ; Mutlu, O ; Asadi, H ; Sharif University of Technology
    Association for Computing Machinery, Inc  2018
    Abstract
    In recent years, high interest in using Virtual Machines (VMs) in data centers and cloud computing has significantly increased the demand for high-performance data storage systems. A straightforward approach to providing a high-performance storage system is using Solid-State Drives (SSDs). Inclusion of SSDs in storage systems, however, imposes significantly higher cost compared to Hard Disk Drives (HDDs). Recent studies suggest using SSDs as a caching layer for HDD-based storage subsystems in virtualized platforms. Such studies neglect to address the endurance and cost of SSDs, which can significantly affect the efficiency of I/O caching. Moreover, previous studies only configure the cache... 

    ReCA: An efficient reconfigurable cache architecture for storage systems with online workload characterization

    , Article IEEE Transactions on Parallel and Distributed Systems ; Volume 29, Issue 7 , 2018 , Pages 1605-1620 ; 10459219 (ISSN) Salkhordeh, R ; Ebrahimi, S ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2018
    Abstract
    In recent years, Solid-State Drives (SSDs) have gained tremendous attention in computing and storage systems due to significant performance improvement over Hard Disk Drives (HDDs). The cost per capacity of SSDs, however, prevents them from entirely replacing HDDs in such systems. One approach to effectively take advantage of SSDs is to use them as a caching layer to store performance critical data blocks in order to reduce the number of accesses to HDD-based disk subsystem. Due to characteristics of Flash-based SSDs such as limited write endurance and long latency on write operations, employing caching algorithms at the Operating System (OS) level necessitates to take such characteristics... 

    An analytical model for performance and lifetime estimation of hybrid DRAM-NVM main memories

    , Article IEEE Transactions on Computers ; Volume 68, Issue 8 , 2019 , Pages 1114-1130 ; 00189340 (ISSN) Salkhordeh, R ; Mutlu, O ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    Emerging Non-Volatile Memories (NVMs) have promising advantages (e.g., lower idle power, higher density, and non-volatility) over the existing predominant main memory technology, DRAM. Yet, NVMs also have disadvantages (e.g., longer latencies, higher active power, and limited endurance). System architects are therefore examining hybrid DRAM-NVM main memories to enable the advantages of NVMs while avoiding the disadvantages as much as possible. Unfortunately, the hybrid memory design space is very large and complex due to the existence of very different types of NVMs and their rapidly-changing characteristics. Therefore, optimization of performance and lifetime of hybrid memory based... 

    An efficient hybrid I/O caching architecture using heterogeneous SSDs

    , Article IEEE Transactions on Parallel and Distributed Systems ; Volume 30, Issue 6 , 2019 , Pages 1238-1250 ; 10459219 (ISSN) Salkhordeh, R ; Hadizadeh, M ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    Storage subsystem is considered as the performance bottleneck of computer systems in data-intensive applications. Solid-State Drives (SSDs) are emerging storage devices which unlike Hard Disk Drives (HDDs), do not have mechanical parts and therefore, have superior performance compared to HDDs. Due to the high cost of SSDs, entirely replacing HDDs with SSDs is not economically justified. Additionally, SSDs can endure a limited number of writes before failing. To mitigate the shortcomings of SSDs while taking advantage of their high performance, SSD caching is practiced in both academia and industry. Previously proposed caching architectures have only focused on either performance or endurance... 

    Evaluating reliability of SSD-Based I/O caches in enterprise storage systems

    , Article IEEE Transactions on Emerging Topics in Computing ; 2019 ; 21686750 (ISSN) Ahmadian, S ; Taheri, F ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss... 

    A modeling framework for reliability of erasure codes in SSD arrays

    , Article IEEE Transactions on Computers ; Volume 69, Issue 5 , May , 2020 , Pages 649-665 Kishani, M ; Ahmadian, S ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2020
    Abstract
    Emergence of Solid-State Drives (SSDs) have evolved the data storage industry where they are rapidly replacing Hard Disk Drives (HDDs) due to their superiority in performance and power. Meanwhile, SSDs have reliability issues due to bit errors, bad blocks, and bad chips. To help reliability, Redundant Array of Independent Disks (RAID) configurations, originally proposed to increase both performance and reliability of HDDs, are also applied to SSD arrays. However, the conventional reliability models of HDD RAID cannot be intactly applied to SSD arrays, as the nature of failures in SSDs are totally different from HDDs. Previous studies on the reliability of SSD arrays are based on the... 

    Dependability analysis of data storage systems in presence of soft errors

    , Article IEEE Transactions on Reliability ; Volume 68, Issue 1 , 2019 , Pages 201-215 ; 00189529 (ISSN) Kishani, M ; Tahoori, M ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    In recent years, high availability and reliability of data storage systems (DSS) have been significantly threatened by soft errors occurring in storage controllers. Due to their specific functionality and hardware-software stack, error propagation and manifestation in DSS is quite different from general-purpose computing architectures. To the best of our knowledge, no previous study has examined the system-level effects of soft errors on the availability and reliability of DSS. In this paper, we first analyze the effects of soft errors occurring in the server processors of storage controllers on the entire storage system dependability. To this end, we implement the major functions of a... 

    Evaluating reliability of SSD-Based I/O caches in enterprise storage systems

    , Article IEEE Transactions on Emerging Topics in Computing ; 2019 ; 21686750 (ISSN) Ahmadian, S ; Taheri, F ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss... 

    Improvements of image-steganalysis using boosted combinatorial classifiers and gaussian high pass filtering

    , Article 2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008, Harbin, 15 August 2008 through 17 August 2008 ; 2008 , Pages 1508-1511 ; 9780769532783 (ISBN) Asadi, N ; Jamzad, M ; Sajedi, H ; Sharif University of Technology
    2008
    Abstract
    Powerful universal steganalyzers were proposed in the literature during the past few years. In addition some studies have been conducted on improvements of current steganalysis results using information fusion techniques, merging available feature vectors, etc. This paper presents two independent ideas, which can be used together, to obtain higher accuracy in detecting stego images. First, we propose the use of boosted fusion methods to aggregate outputs of multiple steganalyzers. Second, we investigate how passing high frequencies through filtering can enhance the results of steganalysis techniques. In this work, it is shown that, through different tests over the state-of-the-art... 

    Evaluating reliability of SSD-Based I/O caches in enterprise storage systems

    , Article IEEE Transactions on Emerging Topics in Computing ; Volume 9, Issue 4 , 2021 , Pages 1914-1929 ; 21686750 (ISSN) Ahmadian, S ; Taheri, F ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2021
    Abstract
    I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and non-volatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss... 

    Evaluating reliability of SSD-Based I/O caches in enterprise storage systems

    , Article IEEE Transactions on Emerging Topics in Computing ; Volume 9, Issue 4 , 2021 , Pages 1914-1929 ; 21686750 (ISSN) Ahmadian, S ; Taheri, F ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2021
    Abstract
    I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and non-volatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss...