Sharif Digital Repository

A high speed, high resolution switched-current sample and hold (SI S/H) based on a new class AB transconductance stage is presented. Simulations performed on the SI S/H in standard 0.18um CMOS technology with 1.5v supply voltage indicate low power dissipation, high sampling speed and high SNR. © 2006 IEEE  

Purpose: The purpose of this paper is to present and evaluate the performance of innovation systems by considering two indicators of efficiency and effectiveness. The scope of the evaluation is globally and due to the situation of each country, the suggested strategies are proposed to maintain the status quo or move toward the desired situation for countries. Design/methodology/approach: The approach is to compare and benchmark the countries in terms of the efficiency and effectiveness of their innovation system. The Global Innovation Index report’s input-to-output ratio and the global competitiveness report are used for the assessment. Findings: The findings indicate that countries such as... 

A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power  

Purpose: The purpose of this paper is to present and evaluate the performance of innovation systems by considering two indicators of efficiency and effectiveness. The scope of the evaluation is globally and due to the situation of each country, the suggested strategies are proposed to maintain the status quo or move toward the desired situation for countries. Design/methodology/approach: The approach is to compare and benchmark the countries in terms of the efficiency and effectiveness of their innovation system. The Global Innovation Index report’s input-to-output ratio and the global competitiveness report are used for the assessment. Findings: The findings indicate that countries such as... 

This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,... 

In this paper, an area-efficient LNA with on-chip input matching circuit utilizing an active inductor is presented. The active inductor is implemented based on the gyrator structure and its noise is improved by employing a feed-forward path (FFP). The overall low-noise performance of the LNA is achieved by cancelling the inductor noise through an additional FFP. It is shown that the proposed LNA circuit is capable of achieving low-noise performance with wideband tuning at the input in a small die area. A 0.32- to 1-GHz LNA has been designed and fabricated in a standard 0.18-μm CMOS technology. The LNA occupies a die area of less than 0.1 mm 2. The measured results show noise figure of... 

A new method to detect leakage in a water-filled plastic pipe is proposed. In this method, a leakage signal-signature in time domain is first captured by monitoring the Short Time Fourier Transforms (STFT) of AE (Acoustic Emission) signals over a relatively long time-interval. The captured signal is then used to find a mother wavelet (tuned wavelet) for the best signal localization in time and frequency domains. The technique for AE signal detection using tuned wavelet is then described. Practical application of the method proposed herein is then presented using a water-filled plastic pipe as a case study. Signals generated from this experimental setup are collected to identify leakage... 

It is shown that negative capacitance (NC) circuits can be systematically used to improve the gain-bandwidth product of the operational amplifiers (opamps). The NC circuit moves the nondominant pole of the opamp to higher frequency by decreasing the parasitic capacitance of the critical node. The impedance at the input of the NC circuits is neither purely capacitive nor negative at all frequencies. A design guide is presented by deriving the circuit model for a conventional NC circuit and investigating the extent of the improvement that can be achieved in a circuit by the use of the NC circuit. The model is then used to present the design guide for widebanding the multistage opamps with... 

The effects of resonator topology on the phase noise of LC oscillators are studied in this paper. It is shown that there is a neglected factor that can considerably influence the phase noise behavior of the oscillator. We designate this factor as the Inductance Energy Factor (IEF), which directly depends on the topology of the resonator. It is shown that through proper design of the resonator for a better IEF, the oscillator phase noise can be improved. It is also shown that by modifying the resonator structure to improve IEF, the phase noise does not have to be constrained by the minimum realizable inductance and its maximum quality factor. Therefore, the power-phase noise trade-off remains... 

Elimination of the surface acoustic wave (SAW) filter from the input of a receiver can render it extremely vulnerable to various blockers and interferers. The presence of large out-of-band (OOB) blockers will result in the required linearity of the SAW-less receiver to be considerably higher than that of the conventional receivers with the input SAW filter. The ever-present undesirable signals that arise in the absence of the input SAW filter can be divided into two classes of far and near OOB blockers and interferers. Removal of these harmful signals requires two distinct approaches according to their nature. Two different methods for blocker and interferer rejection are introduced in this... 

In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply. © 2007 IEEE  

In this paper a new technique called switched-resistor is used as an alternative to switched-capacitor circuits in a low-voltage low-power high-speed A/D converter. Simulation results for an 8-bit 150MS/s pipeline ADC are presented. This converter consumes 20mW from a 1.8V supply and provides an ENOB of 7.5bit. © 2007 IEEE  

In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

A new technique for improving the performance of low-voltage folding ADC's by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input-output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power... 

Currently, there are no studies investigating the issue of speed optimization of Gain-Boosted Cascode Amplifier in low voltage applications. This is mainly because of the complicated transfer function of high-swing Gain-Boosted Cascode Amplifier structures. This paper proposes a novel and generic model for this amplifier and presents a thorough analysis of its behavior. The aim of this optimization is to eliminate the well-known slow timing component in the step response and obtain the minimum achievable settling time. An ultra high-speed amplifier is presented finally  

This letter presents a new approach to low-power, low-latency, and frequency-selective wake-up receivers. A novel architecture is introduced to achieve frequency domain selectivity, including analog techniques, that enable data detection without the need for power-hungry digital processing. A two-mode duty cycling is also utilized, which helps reduce the power consumption of the receiver significantly with negligible latency. A prototype of the proposed receiver is fabricated and verified in a 180-nm CMOS process. The fabricated chipset achieves a sensitivity of-84.9 dBm with 4.32-ms wake-up latency and drains an average current of 12.2 μ text A}. Interference tests show an outstanding... 

Wake-up receivers (WuRX) have recently played a prominent role in many applications, such as the Internet of Things (1oT), Wireless Sensor Networks (WSN), and Wireless Body Area Networks (WBAN). In such systems, relying on limited battery energy for their functionality, the main receiver cannot run continuously because of its high power consumption. In most state-of-the-art WuRXs, the focus is on power consumption and sensitivity. in applications operating in dense environments such as the 915MHz1SM band, considering the congested activity of numerous radios, in-band frequency selectivity becomes imperative as well. Few state-of-theart WuRXs achieve a somehow considerable in-band...