Sharif Digital Repository

Future GPUs should have larger L2 caches based on the current trends in VLSI technology and GPU architectures toward increase of processing core count. Larger L2 caches inevitably have proportionally larger power consumption. In this article, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology. Due to its high-density and low-power characteristics, STT-RAM technology can be utilized in GPUs where numerous cores leave a limited area for on-chip memory banks. They have, however, two important issues, high energy and latency of write operations, that have to be addressed. Low retention time STT-RAMs can... 

The failure of Dennard scaling has led to the utilization wall that is the source of dark silicon and limits the percentage of a chip that can actively switch within a given power budget. To address this issue, a structure is needed to guarantee the limited power budget along with providing sufficient flexibility and performance for different applications with various communication requirements. In this article, we present a generalpurpose platform for future many-core Chip-Multiprocessors (CMPs) that benefits from the advantages of clustering, Network-on-Chip (NoC) resource sharing among cores, and power gating the unused components of clusters. We also propose two task mapping methods for... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,... 

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

With technology advances and the emergence of new fabrication and VLSI technologies, current and future chip multiprocessors (CMPs) are expected to have tens to hundreds of processing elements and Gigabytes of on-chip caches, which are connected by a high bandwidth network-on-chip (NoC). Unfortunately, due to limited power budget of a computing system, specially for its processing element(s), it is impossible to keep all cores, caches, and network elements working at highest voltage level—that would resulted in dark silicon computing era, where by employing system-level or architecture-level techniques, one can keep a great portion of a CMP elements OFF (or in dim mode) to meet the power... 

Modeling and analysis of information system vulnerabilities helps us to predict possible attacks to networks using the network configuration and vulnerabilities information. As a fact, exploiting most of vulnerabilities result in access rights alteration. In this paper, we propose a new vulnerability analysis method based on the Take-Grant protection model. We extend the initial Take-Grant model to address the notion of vulnerabilities and introduce the vulnerabilities rewriting rules to specify how the protection state of the system can be changed by exploiting vulnerabilities. Our analysis is based on a bounded polynomial algorithm, which generates the closure of the Take-Grant graph... 

We study the translocation of stiff polymers through a nanopore, driven by the chemical-potential gradient exerted by binding proteins (chaperones) on the trans side of the pore. Bound chaperones prevent backsliding through the pore and, therefore, partially rectify the polymer passage. We show that the sequence of chain monomers with different binding affinity for the chaperones significantly affects the translocation dynamics. In particular, we investigate the effect of the nearest-neighbor adjacency probability of the two monomer types. Depending on the magnitude of the involved binding energies, the translocation speed may either increase or decrease with the adjacency probability. We... 

Combining the advection-diffusion equation approach with Monte Carlo simulations we study chaperone driven polymer translocation of a stiff polymer through a nanopore. We demonstrate that the probability density function of first passage times across the pore depends solely on the Péclet number, a dimensionless parameter comparing drift strength and diffusivity. Moreover it is shown that the characteristic exponent in the power-law dependence of the translocation time on the chain length, a function of the chaperone-polymer binding energy, the chaperone concentration, and the chain length, is also effectively determined by the Péclet number. We investigate the effect of the chaperone size on... 

The amount of rippling in graphene sheets is related to the interactions with the substrate or with the suspending structure. Here, we report on an irreversibility in the response to forces that act on suspended graphene sheets. This may explain why one always observes a ripple structure on suspended graphene. We show that a compression-relaxation mechanism produces static ripples on graphene sheets and determine a peculiar temperature Tc, such that for T