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    Toward on-chip network security using runtime isolation mapping

    , Article ACM Transactions on Architecture and Code Optimization ; Volume 16, Issue 3 , 2019 ; 15443566 (ISSN) Bayat Sarmadi, M ; Sarmadi, S. B ; Hessabi, S ; Sharif University of Technology
    Association for Computing Machinery  2019
    Abstract
    Many-cores execute a large number of diverse applications concurrently. Inter-Application interference can lead to a security threat as timing channel attack in the on-chip network. A non-interference communication in the shared on-chip network is a dominant necessity for secure many-core platforms to leverage the concepts of the cloud and embedded system-on-chip. The current non-interference techniques are limited to static scheduling and need router modification at micro-Architecture level. Mapping of applications can effectively determine the interference among applications in on-chip network. In this work, we explore non-interference approaches through run-Time mapping at software and... 

    FPGA-based protection scheme against hardware trojan horse insertion using dummy logic

    , Article IEEE Embedded Systems Letters ; Volume 7, Issue 2 , 2015 , Pages 46-50 ; 19430663 (ISSN) Khaleghi, B ; Ahari, A ; Asadi, H ; Bayat-Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed scheme, we identify the unused resources at the device layout-level and offer dummy logic cells for different resources. The proposed HTH protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that by employing the proposed HTH... 

    Secure two-party computation using an efficient garbled circuit by reducing data transfer

    , Article 8th International Conference on Applications and Techniques in Information Security, ATIS 2017, 6 July 2017 through 7 July 2017 ; Volume 719 , 2017 , Pages 23-34 ; 18650929 (ISSN); 9789811054204 (ISBN) Yalame, M. H ; Farzam, M. H ; Bayat Sarmadi, S ; Sharif University of Technology
    Springer Verlag  2017
    Abstract
    Secure computation has obtained significant attention in the literature recently. Classic architectures usually use either the Garbled Circuit (GC) or the Goldreich-Micali-Wigderson (GMW) protocols. So far, to reduce the complexity of communications in these protocols, various methods have been proposed. The best known work in both methods reduces the communication up to almost 2k-bits (k is the symmetric security parameter) for each AND gate, and using XOR gate is free. In this paper, by combining GC and GMW, we propose a scheme in the semi-honest adversary model. This scheme requires an Oblivious Transfer (OT) and a 2-bit data transfer for each AND gate, keeping XOR gates free. The... 

    High-throughput low-complexity systolic montgomery multiplication over GF(2m) Based on Trinomials

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 62, Issue 4 , January , 2015 , Pages 377-381 ; 15497747 (ISSN) Bayat Sarmadi, S ; Farmani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Cryptographic computation exploits finite field arithmetic and, in particular, multiplication. Lightweight and fast implementations of such arithmetic are necessary for many sensitive applications. This brief proposed a low-complexity systolic Montgomery multiplication over GF(2m). Our complexity analysis shows that the area complexity of the proposed architecture is reduced compared with the previous work. This has also been confirmed through our application-specific integrated circuit area and time equivalent estimations and implementations. Hence, the proposed architecture appears to be very well suited for high-throughput low-complexity cryptographic applications  

    Fault-resilient lightweight cryptographic block ciphers for secure embedded systems

    , Article IEEE Embedded Systems Letters ; Vol. 6, issue. 4 , 2014 , pp. 89-92 ; ISSN: 19430663 Mozaffari Kermani, M ; Tian, K ; Azarderakhsh, R ; Bayat Sarmadi, S ; Sharif University of Technology
    2014
    Abstract
    The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

    A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration

    , M.Sc. Thesis Sharif University of Technology Shekofteh, Nastaran (Author) ; Bayat-Sarmadi, Siavash (Supervisor)
    Abstract
    Hardware Trojans have emerged as a major concern for integrated circuits in recent years. As a result, detecting Trojans has become an important issue in critical applications, such as finance and health. In this work, a trusted platform for detecting Trojans in FPGA bitstreams is presented. The proposed methodology takes advantage of increased Trojan activation, caused by transition aware partitioning of the circuit, while it benefits partial reconfiguration feature of FPGAs to reduce area overhead. Simulation results, performed for the transition probability thresholds of 〖10〗^(-4) and 〖2×10〗^(-5), show that this method increases the ratio of the number of transitions in the Trojan... 

    Performance Evaluation of Physical Unclonable Functions and Proposing a Scheme on FPGA

    , M.Sc. Thesis Sharif University of Technology Ramezani, Alireza (Author) ; Bayat-Sarmadi, Siavash (Supervisor)
    Abstract
    In recent years, in addition to traditional cryptographic blocks, a hardware blocks in this work namely PUF, has been used mostly for chip ID generation, authentication and so on. In this work we study recent proposed PUFs and their implementations on FPGA, and the measurement of quality metrics on them. Some of most important characteristics of PUFs are unpredictability, reliability, number of challenge response pairs and area. According to experiments that have been performed in this study and also according to previous work, one high-quality PUF in term of uniqueness and reliability is Ring Oscillator PUF. However, the disadvantage of this PUF is small number of challenge and response... 

    Increasing BIOS Trust in Personal Computers Using Reconfigurable Devices

    , M.Sc. Thesis Sharif University of Technology Eslampanah, Marziye (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Due to the expansion of digital system threats, trusted computation with a new approach for countering such threats has emerged. This approach is based on using a hardware module for implementing a trusted platform (TPM). TPM includes a chipset and the trusted systems core. Nowadays many of mobile computers do include this technology. This hardware creates trust using a trust chain and expanding this trust to other parts of the system. The starting point in this chain is the computer BIOS. BIOS is the first code that the system usually executes. One of the most powerful recent attacks on computer systems is to infect the BIOS and other firmware. One of such complicated attacks is the rootkit... 

    Efficient Implementation of Post-Quantum Cryptography Based on Learning with Errors

    , Ph.D. Dissertation Sharif University of Technology Ebrahimi, Shahriar (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Public key encryption (PKE) cryptography plays a big role in securing communication channels of internet. The security of every PKE scheme is usually based on a hard problem that has no polynomial time solution using any computational structure. However, widely used classic PKE schemes such as RSA or ECC, are based on hard problems that have polynomial solutions using a quantum computer. Therefore, such PKE schemes will not be secure in post-quantum era. Among quantum-resistant schemes, lattice-based cryptography and especially learning with errors (LWE) problem have gained high attention due to their low computational complexity. In this thesis, different LWE-based cryptosystems are... 

    Implementation of an IoT Edge Computing Module in Compliance with TPM Standards

    , M.Sc. Thesis Sharif University of Technology Hasanizadeh, Parisa (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Cloud computing has a significant role in expanding applications of the Internet of Things (IoT). Currently, applications such as virtual reality and augmented reality require low latency, which is not achievable using traditional cloud computing in some scenarios. Edge computing is a new approach in IoT, which solves some of the limitations of the cloud computing by extending and developing its operations. Reducing response time and network traffic are some of the most important achievements of edge computing. Despite of its numerous advantages over cloud computing, edge computing faces serious challenges such as virtualization, implementation infrastructure, resource allocation and task... 

    Improving Remote Attestation Techniques for IoT Devices using Physical Model

    , M.Sc. Thesis Sharif University of Technology Salehi, Mohsen (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Due to the widespread growth in the use of IoT devices, authors consider these devices as an attractive target platform. Several approaches have been proposed to defend IoT devices against various attacks. However, most of them suffer from some shortcomings such as being computationally expensive, not being general, or not being robust enough.Due to the attacks such as firmware modification and the existence of computational limitations, the use of local approaches is inefficient. Another approach is to use remote attestation techniques, which are divided into two categories, static and dynamic. However, static detection techniques are vulnerable to runtime attacks. Furthermore, existing... 

    Customizing a Privacy-Preserving Blockchain-Based Distributed Ledger for Second-Price Auction Smart Contract

    , M.Sc. Thesis Sharif University of Technology Mirzaei, Amir (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    A distributed ledger is a method of digital data storage and sharing in different places, and the blockchain technology is a way of implementing a distributed ledger. This technology has been employed in many of the cryptocurrencies like Ethereum to store transactions. In addition to storing transactions, Ethereum deploys scripts called smart contracts that are automatically executable. These scripts execute transparently and without preserving the privacy of participants. On the other hand, confidentiality and privacy are among the important components in data, network, and system security. Models such as Hawk and Enigma have been presented to obtain privacy-preserving in smart contracts;... 

    Network Traffic Reduction in Internet of Things Using Reconfigurable Cache based on Workload Characterization

    , M.Sc. Thesis Sharif University of Technology Rezaei, Rezvan (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Nowadays, with the advancement of internet of things, The number of nodes within the network has increased and there is huge traffic in these networks despite the small volume of data sent and received each node. The current architecture of the Internet network does not have the functionality required for Internet of things, as a result of designing a new architecture for Internet - based Internet of things. Content - based network is a new architecture introduced to the Internet, and its purpose is to change the network from host-centric to content-centric. One of the features of content-based networks is the use of in network caching that helps increase productivity and reduce the traffic... 

    Implementation of Remote Attestation Mechanism on Internet of Things End-Nodes using TPM

    , M.Sc. Thesis Sharif University of Technology Daghlavi, Khaled (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Today Internet of Things (IoT) applications are growing rapidly around us and alongside this trend, the topics of security and trust in this field are getting more serious. A big part of this field is composed of embedded systems. Remote attestation is a prominent security option in regards of attesting to the integrity of these type of systems and consequently establishing trust remotely. Remote attestation has been an active field of research to attest different type of systems against various types of threats. A noteworthy security hardware, enabling this type of process, is the Trusted Platform Module (TPM). Incorporating this chip in traditional personal computers for security purposes... 

    Reliable concurrent error detection architectures for extended euclidean-based division over (2m)

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Vol. 22, Issue. 5 , 2014 , pp. 995-1003 Mozaffari-Kermani, M ; Azarderakhsh, R ; Lee, C. Y ; Bayat-Sarmadi, S ; Sharif University of Technology
    2014
    Abstract
    The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and digital signature algorithms utilize this operation in their structures. Although much study is performed to realize the EEA in hardware efficiently, research on its reliable implementations needs to be done to achieve fault-immune reliable structures. In this regard, this paper presents a new concurrent error detection (CED) scheme to provide reliability for the aforementioned sensitive and... 

    Systolic gaussian normal basis multiplier architectures suitable for high-performance applications

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 23, Issue 9 , 2015 , Pages 1969-1972 ; 10638210 (ISSN) Azarderakhsh, R ; Kermani, M. M ; Bayat Sarmadi, S ; Lee, C. Y ; Sharif University of Technology
    2015
    Abstract
    Normal basis multiplication in finite fields is vastly utilized in different applications, including error control coding and the like due to its advantageous characteristics and the fact that squaring of elements can be obtained without hardware complexity. In this brief, we present decomposition algorithms to develop novel systolic structures for digit-level Gaussian normal basis multiplication over GF (2m). The proposed architectures are suitable for high-performance applications, which require fast computations in finite fields with high throughputs. We also present the results of our application-specific integrated circuit synthesis using a 65-nm standard-cell library to benchmark the... 

    Fast prototyping with co-operation of simulation and emulation

    , Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) ; Volume 2438 LNCS , 2002 , Pages 15-25 ; 03029743 (ISSN); 3540441085 (ISBN); 9783540441083 (ISBN) Bayat Sarmadi, S ; Miremadi, S. G ; Asadi, G ; Ejlali, A. R ; Sharif University of Technology
    Springer Verlag  2002
    Abstract
    A method for simulation-emulation co-operation of Verilog and VHDL models is presented. The method is based on using Programming Language Interface (PLI) to achieve speedup in prototyping and to facilitate the communication between an emulator and a simulator. The PLI technique is implemented for both Verilog and VHDL models. The results show that this simulation-emulation co-operation method can significantly reduce the simulation time of a design implemented by VHDL codes as well as Verilog codes. © Springer-Verlag Berlin Heidelberg 2002  

    Towards side channel secure cyber-physical systems

    , Article CSI International Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2018, 9 May 2018 through 10 May 2018 ; 9-10 May , 2018 , Pages 31-38 ; 9781538614754 (ISBN) Ashrafiamiri, M ; Afandizadeh Zargari, A. H ; Farzam, S. M. H ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    Cyber-physical systems contain networked embedded systems. Such systems may implement cryptographic algorithms for processing and/or communication. Therefore, they can be prone to side-channel attacks. Differential power analysis is one of such attacks, which is considered among the most serious threats against cryptographic devices. Various metrics have been proposed to evaluate the resistance of different implementations against these attacks. Some of these metrics need side-channel attacks to be conducted and depend on the considered power model. Due to the vast variety of proposed side-channel attacks and power models, comprehensively evaluating a design under these metrics is commonly... 

    High Speed Implementation of Finite Field Multiplier Suitable for Isogeny-Based Protocols

    , M.Sc. Thesis Sharif University of Technology Alivand, Armin (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Classic public key cryptographic systems are based on difficult mathematical problems that will lose their security with the advent of high-speed quantum computers. Isogeny-based cryptography is one of the five main methods in post-quantum cryptography, the hard problem of which is finding large-degree isogenies between elliptic curves. The most important advantage of isogeny-based protocols is the shorter public key length and the main problem is their low speed and low performance compared to other cryptographic systems. Due to the fact that these protocols are implemented on a finite field using basic operations, such as multiplication, squaring, addition, and subtraction, improving the... 

    Enhancing A RISC-V Based Processor to Support Lattice-based Post-uantum Cryptography

    , M.Sc. Thesis Sharif University of Technology Hadayeghparast, Shahriar (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    The amount of data over networks are increasing rapidly, and accordingly, smart devices are being encountered severe challenges by the advancement of security threats. In order to create safe communications among smart devices, employing public-key cryptography is needed. But, public-key and classic cryptography, such as RSA, have high computation complexities and are not resistant to quantum attacks. Due to mentioned reasons, using these types of cryptography algorithms in internet-of-things (IoT) devices is unreasonable. In the past decade, lattice-based cryptography has been one of the pioneer post-quantum cryptography members, which benefits from comparatively lower computational...